Search - pn VHDL

Search - pn VHDL - List

[Other resource] pn_generator DL : 0: PN码发生器的matlab程序，对于写vhdl代码有很重要得参考价值
Update : 2008-10-13 Size : 841byte Publisher : ylt
[Other] pn DL : 1: 用VHDL语言编写的PN码产生程序，希望对大家有所帮助
Update : 2008-10-13 Size : 586.11kb Publisher : 王权
[Other resource] PN DL : 1: 利用vhdl语言编程实现的pn码产生.在quartus ii中通过
Update : 2008-10-13 Size : 87.9kb Publisher : zhangtian
[matlab] pn_generator DL : 0: PN码发生器的matlab程序，对于写vhdl代码有很重要得参考价值-PN code generator matlab procedures, write VHDL code for a very important reference value was
Update : 2025-02-17 Size : 1kb Publisher : ylt
[Other] pn DL : 0: 用VHDL语言编写的PN码产生程序，希望对大家有所帮助-VHDL language used PN code generation process, I hope all of you to help
Update : 2025-02-17 Size : 586kb Publisher : 王权
[Software Engineering] 22 DL : 0: 介绍了基于伪码测距的某定位系统的设计方案，简要分析了伪码测距的原理，研究了用FPGA实现伪码的捕获与跟踪的方法。-Pseudo-code based on the introduction of a positioning system location design scheme, a brief analysis of the principle of pseudo-code ranging study using the FPGA realization of PN code acquisition and tracking method.
Update : 2025-02-17 Size : 50kb Publisher : 王晨磊
[VHDL-FPGA-Verilog] PN DL : 0: 利用vhdl语言编程实现的pn码产生.在quartus ii中通过-The use of VHDL language programming code generated realize the pn. Quartus ii adopted in
Update : 2025-02-17 Size : 88kb Publisher : zhangtian
[VHDL-FPGA-Verilog] pn DL : 1: 用Verilog语言生成7位的小m序列，产生pn码-Verilog language used to generate seven small m sequence code generated pn
Update : 2025-02-17 Size : 2kb Publisher : 楚鹤
[matlab] pn_gen_vhd_211 DL : 0: 通信中常用的PN序列产生器的源代码全部打包-Communications commonly used in PN sequence generator, the source code of all packaged
Update : 2025-02-17 Size : 126kb Publisher : jinyong
[VHDL-FPGA-Verilog] Simulation-and-FPGA-Implementation-of-DigitalDBPSK DL : 0: 文章介绍了系统的硬件电路原理与具体实现方法，其中主要包括载波恢复电路，PN 码捕获电路和跟踪电路，并针对Xilinx 公司FPGA 的特点，对各电路的实现进行优化设计，在不影响系统稳定性和精度的前提下，减少硬件资源消耗，提高硬件利用率。设计利用Verilog 硬件描述语言完成，通过后仿真验证电路正确性，并给出综合结果。-This paper introduces the system' s hardware circuit principle and the specific implementation methods, which mainly include the carrier recovery circuit, PN code acquisition circuit and track circuits, and FPGA for Xilinx company characteristics, the implementation of the circuit to optimize the design, without affecting the system stability and precision under the premise of reduced hardware resource consumption, improve hardware utilization. Designed using Verilog Hardware Description Language finish, after the passage of the correctness of circuit simulation, and give General results.
Update : 2025-02-17 Size : 984kb Publisher : mayuan
[VHDL-FPGA-Verilog] pn_generator DL : 0: FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。-FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
Update : 2025-02-17 Size : 3kb Publisher : 胡佳
[VHDL-FPGA-Verilog] PN_code_capture_and_tracing DL : 0: 一个完整的pn码捕获与跟踪的VHDL源码,并行匹配滤波器捕获,锁相环跟踪.-A complete pn Code Acquisition and Tracking of the VHDL source code, parallel matched filter to capture, phase-locked loop tracking.
Update : 2025-02-17 Size : 2kb Publisher : 王永俊
[Software Engineering] pn DL : 0: pn码串并结合快速捕获算法的改进与研究，详细介绍了串并结合捕获算法的优点-pn code acquisition algorithm for strings in combination with rapid improvement and research, detailing the string combined with the advantages of capturing algorithm
Update : 2025-02-17 Size : 3.22mb Publisher : 员丽琼
[VHDL-FPGA-Verilog] xapp211 DL : 0: ITS VHDL PROGRAM OF PN SEQUENCE
Update : 2025-02-17 Size : 69kb Publisher : sridhar
[VHDL-FPGA-Verilog] PN4 DL : 0: 语言：VHDL 功能：该PN4序列的特点为将一个4位序列的前两位取异或，再让序列左移一位，用异或的结果作为序列的最后一位。序列周期是15，即15位伪随机序列。其中包括序列的产生模块和检测模块。对于误码检测，首先捕获相位。然后，规定测试的码的总个数，统计这些码中有多少个不能满足PN序列特点的，用计数器统计个数。如果发现误码过多，可能是相位失调，重新捕获相位，再进行误码检测。仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the sequence characteristics of the PN4 a 4-bit sequence of the first two to take different or, let a sequence of left, with the result as a sequence of different or the last one. Sequence cycle is 15, or 15-bit pseudo-random sequence. Including sequence generation module and detection module. For error detection, the first capture phase. Then, provided the total number of test code, statistics, the number of these codes can not meet the characteristics of PN sequences, with the number of counter statistics. If you find too many errors, it may be the phase offset, re-acquisition phase, then the error detection. Simulation tools: modelsim synthesis tool: quartus II
Update : 2025-02-17 Size : 4kb Publisher : huangjiaju
[VHDL-FPGA-Verilog] msk_mod DL : 0: msk 调制解调源码，每符号采样8次。对pn码进行调制后，进行解调，解调过程含：符号差分，中值滤波等过程。-msk modem source code, sample 8 times per symbol. Modulation of the pn code after the demodulation, the demodulation process including: symbol differential, the value of the filtering process.
Update : 2025-02-17 Size : 1kb Publisher : 刘进
[VHDL-FPGA-Verilog] PN7 DL : 0: vhdl语言实现 pn码发生器 dpsk调制以及扩频器-pn code generator vhdl language modulation and spread spectrum devices dpsk
Update : 2025-02-17 Size : 1kb Publisher : kid
[VHDL-FPGA-Verilog] vhdl DL : 0: 串并转换和PN码产生的VHDL程序希望对刚学习VHDL语言的同学有帮助！-And the PN code string and convert VHDL program generated just want students to learn VHDL, help!
Update : 2025-02-17 Size : 1kb Publisher : ls112853
[Voice Compress] VHDL DL : 0: 通信领域里的产生随机PN序列，QPSK调制解调的VHDL代码，适合通信领域的人士使用-Communication in the field of random PN sequence, QPSK modulation and demodulation of the VHDL code, those suitable for use in the field of communications
Update : 2025-02-17 Size : 2kb Publisher : 岳雨豪