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[VHDL-FPGA-Verilog] core_arm.tar

Description: 用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse
Platform: | Size: 655360 | Author: 昭君 | Hits:

[VHDL-FPGA-Verilog] miniMIPS

Description: 这是一个基于mips-I结构的处理器,32bit,冯诺依曼结构-This is based on a MIPS- I structure of the processor, 32bit, von Neumann structure
Platform: | Size: 222208 | Author: tsm998 | Hits:

[VHDL-FPGA-Verilog] Sparc_leon_VHDL

Description: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Platform: | Size: 1873920 | Author: 韩红 | Hits:

[MPI] source

Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated,
Platform: | Size: 6144 | Author: 陈丰 | Hits:

[MPI] MIPS

Description: MIPS处理器的顶层VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS processor top-level VHDL code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[Other] MDCT

Description: MPEG MDCT的一些文章 A design on the vector-processor of MDCT-IMDCT algorithm for digital audio；A fast algorithm of integer MDCT for lossless audio coding-MPEG MDCT articles A design on the vector-processor of MDCT-IMDCT algorithm for digital audio A fast algorithm of integer MDCT for lossless audio coding
Platform: | Size: 5156864 | Author: dingying | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。-Described in VHDL language using single-precision floating-point processor. Web site source code from abroad. Can be achieved single precision floating point addition and subtraction, multiplication.
Platform: | Size: 16384 | Author: WeimuMa | Hits:

[VHDL-FPGA-Verilog] FFT_report

Description: Design Simulation and synthesis of a fft processor using VHDL
Platform: | Size: 362496 | Author: lys | Hits:

[VHDL-FPGA-Verilog] MultiCycleProcessor

Description: 描述：在D2SB FPGA上的多循环RISK处理器 -Description: D2SB FPGA in the multi-cycle processor RISK
Platform: | Size: 796672 | Author: 陈晓 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] asdd

Description: 论文基于FPGA的高速实时FFT处理器设计，给出了详细的设计流程！-Thesis of high-speed FPGA-based real-time FFT processor design, detailed design gives the flow!
Platform: | Size: 157696 | Author: 邓振淼 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera

Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能： （1）在液晶屏上显示时间、日期、状态提示； （2）利用4个按键对时间（时分秒）、日期（年月日）进行设置； （3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock
Platform: | Size: 6460416 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] spi_interface

Description: 介绍了如何用vhdl语言实现处理器的spi接口-Describes how to use VHDL language processor spi interface
Platform: | Size: 496640 | Author: david | Hits:

[VHDL-FPGA-Verilog] verilog_risc

Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前 对这16个数进行排序，从大到小放置在18到33的位置 求出前16个数的平均数，放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。 因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Platform: | Size: 129024 | Author: lyn | Hits:

[Other] ARM_and_Verilog

Description: arm处理器的vhdl源代码编写，可以参考-arm processor VHDL source code to prepare, can refer to
Platform: | Size: 3226624 | Author: 黄伟 | Hits:

[Windows Develop] ce3100-datasheet

Description: 机顶盒 set top box 设计参考。intel media processor CE 3100 .功能非常强大！-STB set top box reference design. intel media processor CE 3100. very powerful!
Platform: | Size: 1342464 | Author: 姚建平 | Hits:

[VHDL-FPGA-Verilog] SYNTHPIC.ZIP

Description: The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting -The Synthetic PICVerion 1.1This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.It is not, and is not intended as, a high fidelity circuit simulation.This package includes the following files. Note that the license agreementis stated in the main VHDL file , PICCPU.VHD and common questions are answeredin the file SYNTHPIC.TXTFiles: README.TXT This file .. SYNTHPIC.TXT Questions and AnswersPICCPU.VHD Main processor VHDL filePICALU.VHD ALU for the PICCPUPICREGS.VHD Data memoryPICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it.TEST2.ASM Another test program. . TEST3.ASM Yet another .. TEST4.ASM Yet another .. TEST5.ASM Yet another .. TEST6.ASM Yet another .. HEX2VHDL.CPP Utility for converting
Platform: | Size: 48128 | Author: likui | Hits:

[VHDL-FPGA-Verilog] FPGA_FFT

Description: 基于FPGA的高速FFT处理器的设计与实现-FPGA-based high-speed FFT Processor Design and Implementation
Platform: | Size: 73728 | Author: 萧球水 | Hits:

[VHDL-FPGA-Verilog] code

Description: 一个8位微处理器的VHDL代码以及testbench-8-bit processor VHDL
Platform: | Size: 8192 | Author: fei | Hits:

[Editor] processor.tar

Description: i need of vhdl code for 32-bit risc processor
Platform: | Size: 48128 | Author: ganesh | Hits:
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