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Description: 基于Verilog-HDL的硬件电路的实现
9.5 脉冲周期的测量与显示
9.5.1 脉冲周期的测量原理
9.5.2 周期计的工作原理
9.5.3 周期测量模块的设计与实现
9.5.4 forever循环语句的使用方法
9.5.5 disable禁止语句的使用方法
9.5.6 时标信号发生模块的设计与实现
9.5.7 周期计的Verilog-HDL描述
9.5.8 周期计的硬件实现
9.5.9 周期测量模块的设计与实现之二
9.5.10 改进型周期计的Verilog-HDL描述
9.5.11 改进型周期计的硬件实现
9.5.12 两种周期计的对比
-based on Verilog-HDL hardware Circuit of 9.5 pulse cycle of measurement and display 9.5.1 pulse cycle 9.5.2 cycle measurement principle, the principle 9.5.3 cycle measurement Module Design and Implementation 9.5.4 statement cycle forever the use 9.5.5 di sable statement ban on the use 9.5.6 at the beacon signal occurred Module Design and Implementation 9.5 .7 cycle of Verilog-HDL description 9.5.8 cycle of hardware 9.5. 9 cycle measurement module design and realization of two 9.5.10 Improved cycle of Verilog- HDL description 9.5.11 Improved cycle of hardware 9.5.12 two cycles of contrast
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Size: 5120 |
Author: 宁宁 |
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Description: This the q p s keying signallling.
just use wid the given pulse to modulate the pulse.-This is the q p s keying signallling.
just use wid the given pulse to modulate the pulse.
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Size: 1024 |
Author: Gaurav |
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