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[VHDL-FPGA-Verilog] PWM_DCmotorControl

Description: 基于VHDL的直流电机的PWM控制程序。-The VHDL-based DC motor PWM control procedures.
Platform: | Size: 193536 | Author: luoqianyou | Hits:

[VHDL-FPGA-Verilog] cpld-pwm

Description: 基于cpld的pwm控制设计 采用vhdl.verilog语言设计 对大家比较有用-CPLD-based control design uses the pwm design vhdl.verilog language more useful for everyone
Platform: | Size: 79872 | Author: emily | Hits:

[VHDL-FPGA-Verilog] CPLD_Design_50

Description: CPLD实用设计50例，非常经典的CPLD设计，包含50个实际的典型应用，涉及直流电机PWM驱动，编码等内容，有了这50例，举一反三，就会了很多应用-50 cases of practical CPLD design, very classic CPLD design, including 50 typical practical applications, involving PWM DC motor driver, coding, etc., with these 50 cases, giving top priority will be a lot of applications
Platform: | Size: 7625728 | Author: 刘工 | Hits:

[VHDL-FPGA-Verilog] moter

Description: VHDL写的PWM发生器，仿真通过，波形基本完美，可以用于直流电机的控制-PWM generator written in VHDL, simulation is passed, the basic waveform perfect, can be used for DC motor control
Platform: | Size: 897024 | Author: dansen | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。 直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Platform: | Size: 37888 | Author: 袁玉佳 | Hits:

[VHDL-FPGA-Verilog] EP1C3_12_1_2_MOTO

Description: 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写，压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
Platform: | Size: 1193984 | Author: deadtomb | Hits:

[VHDL-FPGA-Verilog] DCmotor

Description: 给出了具体的基于FPGA的直流电机PWM控制VHDL程序，可用于毕业设计。-Given a specific FPGA-based DC motor PWM control VHDL program can be used to graduation.
Platform: | Size: 3188736 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] PWM-DCMotor-Control-based-on-VHDL

Description: 基于VHDL的直流电机的PWM控制程序，用vhdl语言写的直流电机控制程序-PWM DC Motor Control Program based on the VHDL
Platform: | Size: 210944 | Author: | Hits:

[VHDL-FPGA-Verilog] VHDL_PWM

Description: 基于VHDL的直流电机的PWM控制程序 PWM型DC／DC变换器控制方法-VHDL-based DC motor PWM control procedures PWM type DC/DC converter control
Platform: | Size: 203776 | Author: 李亚军 | Hits:

[VHDL-FPGA-Verilog] dc-motor-speed-control

Description: 基于VHDL的pwm直流电动机双闭环调速-Pwm dc motor speed control based on VHDL
Platform: | Size: 357376 | Author: ganun | Hits:

[Software Engineering] BLDCM-based-on-NIOS

Description: 基于NIOSII的无刷直流电机控制器设计 庄任勤 大连海事大学 硕士论文 电力电子与电力传动 2009年6月 本文介绍了无刷直流电机的工作原理，研究了无刷直流电机的PWM调制方式，实现了基于Nios软核的无刷直流电机控制系统的SOPC设计。系统硬件包括以FPGA为核心的控制电路和用于电机驱动的三相全桥逆变电路，对FPGA及其外围设备的选择和逆变电路的设计做了大量研究工作。软件设计包括在Quartusn中用vHDL语言生成的位置检测模块、电机控制模块和PID调节器的IP核以及在 SOPCBullder中实现NioSH软核和外围IP核的定制和控制软件的设计。重点对PID调节器的FPGA实现做了一些探讨。 本文针对逆变电路的工作方式，运用PWM调制技术，做了全桥调制和半桥调制实验，并对实验结果进行了分析。实验表明，本无刷直流电机控制系统运行性能良好，调试方便，开关噪音小，升级换代容易，为后续的研究工作提供了基础和借鉴。-June 2009 based on the NIOSII the brushless DC motor controller design the Zhuang Renqin Dalian Maritime University Thesis power electronics and electric drive
Platform: | Size: 3739648 | Author: 午后薄荷 | Hits:

[VHDL-FPGA-Verilog] VHDL-book3

Description: D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mod5cnt：模5计数器的设计 mod10Kcnt：时钟分频器的设计 morsea：任意波生成器的设计 sw2reg：加载开关量到寄存器的设计 shift_reg8：移位数据到移位寄存器的设计 scroll：滚动7段数码显示设计 fib：Fibonacci序列设计 pwm4：PWM控制直流电机设计 pwmg：PWM控制伺服电机位置设计-D_flipflop: 1-bit D flip-flop design D_fllipflop_behav: 4-bit D flip-flop design reg1bit: 1-bit register design reg4bit: 4-bit register design shiftreg4: general shift register design ring_shiftreg4: ring shift register design debounce4: elimination shake circuit design clock_pulse: clock pulse circuit design count3bit_gate: 3-bit counter design count3bit_behav: 3-bit counter design mod5cnt: Mode 5 counter design mod10Kcnt: clock divider design morsea: arbitrary waveform generator design sw2reg: Load switch to register the design shift_reg8: shift data into the shift register design scroll: Scroll 7-segment digital display design fib: Fibonacci Sequence Design pwm4: PWM controlled DC motor design pwmg: PWM servo motor position control design
Platform: | Size: 9017344 | Author: 贾诩 | Hits:

[Other] arm_FPGA

Description: 步进电机、直流电机PWM控制、伺服电机编码器解码vhdl程序-Stepper motor, PWM DC motor control, servo motor encoder decoder VHDL program
Platform: | Size: 25600 | Author: 刘文 | Hits:

[DSP program] DCsources_

Description: PWM generator written in VHDL, simulation is passed, the basic waveform perfect, can be used for DC motor control
Platform: | Size: 24576 | Author: hieu | Hits:

[VHDL-FPGA-Verilog] PWM-IS

Description: control Pulse width modulation (PWM) using VHDL code and Block schematic.the selection switch at the FPGA board is important to control the duty cycle of PWM.For example application that can be used is to control speed dc motor.-control Pulse width modulation (PWM) using VHDL code and Block schematic.the selection switch at the FPGA board is important to control the duty cycle of PWM.For example application that can be used is to control speed dc motor.
Platform: | Size: 1931264 | Author: abdul | Hits:

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