Search - qiangdaqi vhdl

[Other] qiangdaqi

Description: 用VHDL设计的7人的抢答器,优点是代码简单,特别适合初学着作为练习和增强代码编写能力的练习,好处
Platform: | Size: 795 | Author: 遇见 | Hits:

[VHDL-FPGA-Verilog] VHDLverilogshirenqiangdaqi

Description: 用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
Platform: | Size: 5120 | Author: qihuolin | Hits:

Description: 用VHDL设计的7人的抢答器,优点是代码简单,特别适合初学着作为练习和增强代码编写能力的练习,好处-Designed using VHDL Answer 7 people, and the advantages of the code is simple, particularly suitable for the beginner as coding exercises and strengthen the capacity of exercises, the benefits of
Platform: | Size: 1024 | Author: 遇见 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 抢答器。可以直接用QUARTUS2运行，解压无需密码。以前我们做实验的时候用的这个-Answer devices. Can be directly used QUARTUS2 running, unzip without a password. Previous experiments when we used to do this
Platform: | Size: 254976 | Author: catalina | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 实现抢答器功能，30秒的倒数，抢答控制均可以，-Answer to achieve function, 30 seconds of the countdown for the Answer can be controlled,
Platform: | Size: 243712 | Author: 涂亮 | Hits:

[SCM] shuziqiangdaqi

Description: 1. 抢答器同时供8名选手或8个代表队比赛，分别用8个按钮S0 ~ S7表示。 2. 设置一个系统清除和抢答控制开关S，该开关由主持人控制。 3. 抢答器具有锁存与显示功能。即选手按动按钮，锁存相应的编号，并在LED数码管上显示，同时扬声器发出报警声响提示。选手抢答实行优先锁存，优先抢答选手的编号一直保持到主持人将系统清除为止。 4. 抢答器具有定时抢答功能，且一次抢答的时间由主持人设定（如30秒）。当主持人启动"开始"键后，定时器进行减计时，同时扬声器发出短暂的声响，声响持续的时间0.5秒左右。 5. 参赛选手在设定的时间内进行抢答，抢答有效，定时器停止工作，显示器上显示选手的编号和抢答的时间，并保持到主持人将系统清除为止。 6. 如果定时时间已到，无人抢答，本次抢答无效，系统报警并禁止抢答，定时显示器上显示00。
Platform: | Size: 257024 | Author: haiyang | Hits:

[SCM] qiangdaqi

Description: 八路抢答器设计源码功能模块设计带电路图-Answer eight-way design features modular design with source circuit
Platform: | Size: 569344 | Author: 徐小俊 | Hits:

[SCM] qiangdaqi

Description: 四人抢答器设计,具有超前抢答显示报警，20秒倒计时超时抢答报警及加分、减分等功能-Answer four design, with advance Answer show alarm, countdown to 20 seconds of overtime Answer alarm and extra points, reducing the classification function
Platform: | Size: 2048 | Author: 小草 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: VHDL基础数据对象抢答器适合新手-failed to translate
Platform: | Size: 462848 | Author: bniy | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 用verilog编写的抢答器，当主持人宣布“开始比赛”，系统初始化，选手进入“抢答状态”。当某一选手首先按下抢答开关时，相应的指示灯亮，此时抢答器不再接受其他输入信号。电路具有累计分控制（分别用４个４位选手的积分——十六进制数），由主持人控制“加分”。“加分”加分完毕，开始下一轮抢答。电路还可以设有回答问题时间控制。 -Answer using Verilog prepared, and when the host announced the " start game" , the system initialization, players enter the " Answer status." When a player first of all, press the Answer the switch, the corresponding indicator light, when the Answer Explorer no longer accept other input signals. Circuit with a total of sub-control (separately with four players four points- hexadecimal number), by the host control " points." " Add points" add hours after beginning the next round of Answer. Circuit can also be equipped with time control to answer questions.
Platform: | Size: 1103872 | Author: 叶 | Hits:

[SCM] qiangdaqi

Description: 　 (1) 抢答器线路测试功能　　为了保证比赛的正常进行，比赛前需要调试线路能否正常工作。　　 (2) 第一抢答信号的鉴别和锁存功能　　可以判断谁最先抢到回答的资格，其相应的绿灯表示抢答成功，并具有锁存功能，一直到下一题开始。　　 (3) 犯规警示功能　　可以判断出参赛者有没有在主持人读题的期间按下抢答器，有则相应的红灯亮，同时取消其本轮抢答资格。　　 (4) 计时功能　　可以预置时间，可以进行倒计时并且将时间显示出来。　　 (5) 计分功能可以实现加分，并且显示出来 -(1) Answer line testing device in order to ensure the normal game, the need to debug line before the game can work properly. (2) Answer the first to identify and latch signals to determine who can be the first to get the qualifications to answer, and its corresponding Answer green that success and with latch function, until the beginning of the next title. (3) foul warning function can be judged contestants have read in the host during the press Answer questions, and there is a corresponding red light, at the same time cancel the current round of qualifications Answer. (4) The time functions can be preset time, the countdown can be displayed and the time. (5) scoring function points can be achieved and displayed.
Platform: | Size: 956416 | Author: 孙国栋 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 四人抢答器，已通过编译，仿真，包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.
Platform: | Size: 2048 | Author: majianhui | Hits:

[Other] qiangdaqi

Description: 抢答器，用vhdl语言编程，在fpga平台上实现。-Responder, with the vhdl language programming, in fpga platform to achieve.
Platform: | Size: 35840 | Author: 小哇 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 基于VHDL与FPGA的四路抢答器的设计与仿真。主要模块：抢答、竞争冒险、抢答倒计时、加分减分、超时蜂鸣、按键消抖、答题记时等模块-VHDL and FPGA-based four-way Responder Design and Simulation. Main modules: Responder, competition and adventure, answer in the countdown, plus minus points, overtime buzzer, key debounce, and other modules in mind when answering
Platform: | Size: 1540096 | Author: 丫头 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 已VHDL语言实现人抢答器，有抢答计时，答题计时，超时报警功能，通过仿真-VHDL language has been one answer device, there is answer in time, answer time, time-out alarm function, the simulation
Platform: | Size: 4096 | Author: louxy | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 一个关于抢答器的HDL设计，完整源代码 Vhdl编程，编译通过-A Responder on the HDL design, complete source code Vhdl programming, compile
Platform: | Size: 1024 | Author: 陈倩 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 多路抢答器 VHDL语言设计抢答器是各类竞赛常用的仪器设备之一，它能快速、准确地判决并显示出第一抢答者。本文作者采用MAXPLUSII 软件和MAX7000S芯片，提出了一种四路抢答器的设计方案。该方案具有判断准确、硬件电路简单、容易实现等优点。关键字：抢答器竞争 RS触发器 EDA -Multiple Responder Responder VHDL language design competition of various kinds of equipment used, it can quickly and accurately answer in the first sentence and show those. The author uses MAXPLUSII MAX7000S chip software and proposes a four-way Responder design. The program has to determine accurately, the hardware circuit is simple, easy to implement and so on. Keywords: Responder competitive EDA RS flip-flop
Platform: | Size: 80896 | Author: 王天宇 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 基于quartus II 软件用vhdl语言写的抢答器实验源代码、最终生成文件全程奉献-Quartus II software-based language used to write vhdl traffic light test source code, the resulting file full dedication
Platform: | Size: 350208 | Author: 大毛 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 基于可编程软件的抢答器设计，使用的是VHDL语言进行编程-Based on programmable software Responder design,Use VHDL language to program
Platform: | Size: 1184768 | Author: 何雨 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 使用vhdl语言设计的一个四人参加的智力竞赛抢答计时器。当有某一参赛者首先按下抢答开关时，响应显示灯亮并伴有声响，此时抢答器不再接受其他输入信号。电路具有回答问题时间控制功能。要求回答问题时间小于100s（显示为0—99），时间显示采用倒计时方式。当达到限定时间时，的发出声响以示警告。 -Using VHDL language design four people to participate in the quiz answer in the timer. When a participant Press First Responder switch in response to lights and accompanied by sound Responder longer accept other input signal. The circuit has a time control function answered questions. Asked to respond to the problem in less than 100s (for 0-99), time countdown. When the time limit is reached, the audible warning to show.
Platform: | Size: 192512 | Author: 陈小龙 | Hits:

« 12 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Other] qiangdaqi

[VHDL-FPGA-Verilog] VHDLverilogshirenqiangdaqi

[Other] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[SCM] shuziqiangdaqi

[SCM] qiangdaqi

[SCM] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[SCM] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[Other] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

[VHDL-FPGA-Verilog] qiangdaqi

CodeBus www.codebus.net