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[Embeded-SCM Develop] Ddelay DL : 0: 在Quartus下使用D触发器来加入延迟，每个D触发器增加半个周期的延迟，稍加更改可以得到不同的延迟。
Update : 2008-10-13 Size : 369.71kb Publisher : 桃子
[Other] 02-Designing_with_Quartus_II_v5_0 DL : 0: 使用Quartus II 5.0开发指导手册-use Quartus II 5.0 development guidance manual
Update : 2025-02-17 Size : 11.28mb Publisher : KC_P
[source in ebook] Crack_QII60_b178 DL : 0: Quartus II 6.0完全Crack文件-Quartus II 6.0 document completely Crack
Update : 2025-02-17 Size : 6kb Publisher : 江纵海
[Embeded-SCM Develop] Ddelay DL : 0: 在Quartus下使用D触发器来加入延迟，每个D触发器增加半个周期的延迟，稍加更改可以得到不同的延迟。-In Quartus using D flip-flop to join the delay, each D flip-flop raised a half-cycle delay, a little change can be a different delay.
Update : 2025-02-17 Size : 369kb Publisher : 桃子
[VHDL-FPGA-Verilog] 20080618101911140 DL : 0: Quartus_II_7.2_b151破解器.用于Quartus_II_7.2-Crack Quartus_II_7.2_b151 browser. For Quartus_II_7.2
Update : 2025-02-17 Size : 394kb Publisher : ellen
[VHDL-FPGA-Verilog] ADC0809 DL : 0: 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
Update : 2025-02-17 Size : 45kb Publisher : 杨晴飞
[VHDL-FPGA-Verilog] usb-blaster DL : 0: quartus多种USB-bletera 自制下载线！
Update : 2025-02-17 Size : 2.22mb Publisher : 陈长佳
[VHDL-FPGA-Verilog] Quartus2_cracker_72sp2 DL : 0: Quartus 7.2工具软件的破解文件，从中国区总代理处流出。-Quartus 7.2 software tool to break a document from the Department out of the general agent in China.
Update : 2025-02-17 Size : 12kb Publisher : neimty
[VHDL-FPGA-Verilog] analogue-digi-ana-converter DL : 0: design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.
Update : 2025-02-17 Size : 1.33mb Publisher : ak
[VHDL-FPGA-Verilog] DDS DL : 0: 基于quartus的DDS，可以发生正弦波，方波，三角波，附带了顶层文件，注释在程序中-Quartus on the DDS, can occur sine wave, square wave, triangle wave, with the top-level documents, notes in the procedure
Update : 2025-02-17 Size : 76kb Publisher : ivan
[Software Engineering] license DL : 0: Update : 2025-02-17 Size : 360kb Publisher : 赵杰
[VHDL-FPGA-Verilog] DFFquartus DL : 0: D触发器 quartus实现有RTL图-D flip-flop to achieve a RTL Figure quartus
Update : 2025-02-17 Size : 1015kb Publisher : 海到无涯
[VHDL-FPGA-Verilog] FPGA_AD7822 DL : 0: 基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl-A Design of the A/D Convertion Control Module Based on FPGA
Update : 2025-02-17 Size : 56kb Publisher : sxy
[VHDL-FPGA-Verilog] dtrigger DL : 0: 常用触发器——D触发器的VERILOG语言描述，可用Quartus II 9.0 和modelsim环境实现。-Common triggers- D flip-flop of VERILOG language description available Quartus II 9.0 and modelsim environment to achieve
Update : 2025-02-17 Size : 1kb Publisher : 李菲
[VHDL-FPGA-Verilog] DFF_BDF DL : 0: D触发器设计图形输入法,设计软件quartus-Input D flip-flop design graphics, design software quartus
Update : 2025-02-17 Size : 4kb Publisher : wangchenlin2000
[VHDL-FPGA-Verilog] exp1.8_Dflipflop DL : 0: 用VHDL及verylog语言设计一个D触发器，可以在Quartus II中仿真-Language Design with VHDL and verylog a D flip-flop, the Quartus II simulation in
Update : 2025-02-17 Size : 267kb Publisher : davidye
[VHDL-FPGA-Verilog] exp_micro_s DL : 0: 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复！ 2.运行时请注意完整路径： D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题？ 3.1 MODELSIM中w完信号后，run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_in.log窗口。 +号后,输入LOVE CHINA！ 3.4 run 1ms.看波形结果。 3.5 quit -f。 ZHJ 2009/11/9 晚-Quartus project file for Classic exp with MICRO-SEQUENCER:echo uart
Update : 2025-02-17 Size : 4.81mb Publisher : zh
[VHDL-FPGA-Verilog] Part4 DL : 0: RS Latch and D Latch on Quartus
Update : 2025-02-17 Size : 1kb Publisher : Zeny
[VHDL-FPGA-Verilog] Trigger DL : 0: 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
Update : 2025-02-17 Size : 904kb Publisher : baoguocheng
[VHDL-FPGA-Verilog] round DL : 0: 利用实验箱标配的AD_DA板上的D/A数模转换器，模拟一个圆的波形，学习LPM_ROM（1024*10）宏功能模块的定制与使用，最后利用Quartus II完成设计、仿真。-The the experimental box standard AD_DA panel D/A converters, a round analog waveform, learning LPM_ROM (1024* 10) the megafunctions the customization and use last Quartus II to complete the design, simulation.
Update : 2025-02-17 Size : 80kb Publisher : 跳跳鱼

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