Search - quartus 8.

[Other resource] Crack_QII8.0

Description: quartus 8 的内存注册机，已经试验过，非常好用，完全破解。
Platform: | Size: 15428 | Author: 庄保国 | Hits:

[Other Embeded program] FPGA简易3-8译码器

Description: QUARTUS II实现的简易3 8译码器
Platform: | Size: 58634 | Author: yzhh029 | Hits:

[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1024 | Author: 夏社 | Hits:

[VHDL-FPGA-Verilog] Nios II处理器中文参考手册

Description: nios2软件开发手册中文版第8章_MicroC_OSII_tutorial，翻译的不错值得一看-nios2 software development manuals Chinese version of Chapter 8 _MicroC_OSII_tutori al translation of a true eye-catcher
Platform: | Size: 259072 | Author: wang | Hits:

[Software Engineering] quartus_Chinese_Introduction

Description: quartus 软件应用中文教程，包含一些高级的用法等。-quartus Chinese Directory software applications, including some senior usage, and so on.
Platform: | Size: 6616064 | Author: Frank | Hits:

[Other Embeded program] 38encode

Description: 三八译码器的源代码，在quartus II 6.0中进行进行设计的，有vhdl源代码-March 8 decoder source code, in quartus II 6.0 for the design, Source code is vhdl
Platform: | Size: 151552 | Author: 孙彤 | Hits:

[VHDL-FPGA-Verilog] b8bit_adder

Description: 8位的加法器设计，分4个工程完成的，用的是Quartus II软件。-eight of the adder design, four hours to complete the project, using the Quartus II software.
Platform: | Size: 520192 | Author: jk | Hits:

[VHDL-FPGA-Verilog] 8b_10b

Description: vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: | Size: 72704 | Author: 聂样 | Hits:

[VHDL-FPGA-Verilog] KeyBoard

Description: 4*8矩阵键盘的驱动程序。QuartusII5.0编译通过！-4* 8 matrix keyboard driver. QuartusII5.0 compiled through!
Platform: | Size: 231424 | Author: sunhao | Hits:

[Other] 4_in_1

Description: 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。-Cytech latest quartus8.0 the license, including the Quartus II 8.0, NIOS II 8.0 (in the Quartus II
Platform: | Size: 332800 | Author: 王网 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[Other] 80sp1crack

Description: quartus II 8.0sp1 patch破解文件-quartus II 8.0sp1 patch crack file
Platform: | Size: 798720 | Author: 王京 | Hits:

[VHDL-FPGA-Verilog] Crack_QII8.0

Description: quartus 8 的内存注册机，已经试验过，非常好用，完全破解。-quartus 8 Zhuceji memory has been tested, very easy to use, completely broken.
Platform: | Size: 15360 | Author: 庄保国 | Hits:

[Other] Crack_QII72

Description: QUARTUS-7.2的破解软件，可以破解QUARTUS-7.2，能用到2034年。-The crack QUARTUS-7.2 software, can crack QUARTUS-7.2, can be used to in 2034.
Platform: | Size: 337920 | Author: 苏洲 | Hits:

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[Other resource] Crack_QII8.0

[Other Embeded program] FPGA简易3-8译码器

[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序

[VHDL-FPGA-Verilog] Nios II处理器中文参考手册

[Software Engineering] quartus_Chinese_Introduction

[Other Embeded program] 38encode

[VHDL-FPGA-Verilog] b8bit_adder

[VHDL-FPGA-Verilog] 8b_10b

[VHDL-FPGA-Verilog] KeyBoard

[Other] 4_in_1

[VHDL-FPGA-Verilog] risc_cpu

[Other] 80sp1crack

[VHDL-FPGA-Verilog] Crack_QII8.0

[Other] Crack_QII72

[Embeded-SCM Develop] 8-bitdecimalfrequency

[VHDL-FPGA-Verilog] FPGAandSOPC

[VHDL-FPGA-Verilog] FIFO

[VHDL-FPGA-Verilog] The-Duck

[VHDL-FPGA-Verilog] Crack_QII81_FULL_License

[VHDL-FPGA-Verilog] Quartus8.1_licence

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