Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - quartus 9.0

Search list

[VHDL-FPGA-Verilog] GuangShanChi

Description: 光栅尺的四细分和辩向电路，并具有计数器功能，利用Quartus综合，可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to
Platform: | Size: 694272 | Author: 蔡有才 | Hits:

[VHDL-FPGA-Verilog] vhdl_crc

Description: 在quartus中用VHDL语言开发的crc校验-Quartus VHDL language used in the development of CRC Checksum
Platform: | Size: 163840 | Author: 夏杰 | Hits:

[VHDL-FPGA-Verilog] crack_qii90

Description: altera quartus 9 crack working
Platform: | Size: 14336 | Author: sreejith s | Hits:

[Other] Crack_QII90_SP2

Description: Quartus II 9.0 SP2 破解-crack for Quartus II 9.0 SP2
Platform: | Size: 14336 | Author: 胡文静 | Hits:

[Embeded-SCM Develop] fft3

Description: quartus 9.0 中FFT IP核的使用方法附带工程文件和用signaltapII抓到的波形-quartus 9.0 in FFT IP core attached to the use of engineering documents and the use of captured waveform signaltapII
Platform: | Size: 13032448 | Author: hewenlong | Hits:

[VHDL-FPGA-Verilog] learn_dds

Description: 基于quartus ii 9.0的简易dds波形发生器，可以产生正弦，方波，三角波，可变幅，可变频。非常适合学习使用，使用时请按自己的芯片和引脚设置-Quartus ii 9.0 Based on dds simple waveform generator can produce sine, square, triangle wave can be amplitude, frequency can be. Very suitable for learning to use, when used by their chip and pin set
Platform: | Size: 732160 | Author: 陈东旭 | Hits:

[Windows Develop] learn_rom_99multi

Description: 基于quartus ii 9.0的99乘法器，用rom表做成的乘法器可以计算9*9的乘法，并在数码管上显示，使用时请按照自己的芯片和引脚设置。-Quartus ii 9.0 based on 99 multiplier, made by rom multiplier table can calculate the multiplication 9* 9, and in the digital control display, according to their own use when the chip and pin set.
Platform: | Size: 487424 | Author: 陈东旭 | Hits:

[VHDL-FPGA-Verilog] oc_i2c_master_top_v92

Description: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Platform: | Size: 3072 | Author: homeuser | Hits:

[VHDL-FPGA-Verilog] horse_light4

Description: 六种花样的流水灯，从左至右，从右至左，中间向两边，两边向中间，跳格闪烁等。verilog语言编写； 并且扩展容易； 有两个状态机构成实现。quartus 9.0和7.1仿真通过。无错误，无警告。-Six kinds of patterns of flowing water lights, from left to right, from right to left, in the middle to both sides, both sides toward the middle, jumping grid flicker. And expansion easy there are two state agencies into a realization. quartus 9.0 and 7.1 by simulation. Error-free, no warning.
Platform: | Size: 69632 | Author: tangjieling | Hits:

[Other] CDM2.04.16WHQLCertified

Description: altera quartus 9.0 在win7 64位下的下载器驱动-altera quartus 9.0 usb_byteblaster_driver in window7 64
Platform: | Size: 732160 | Author: 王易 | Hits:

[Other] Crack_Quartus+II+9.1

Description: Its crack file for Altera Quartus 9.1
Platform: | Size: 20480 | Author: Giang | Hits:

[VHDL-FPGA-Verilog] DAC

Description: Quartus 9.0 Project of a dual DAC0808 interface.Very simple and clean design, plus Avalon slave interface!
Platform: | Size: 399360 | Author: nada | Hits:

[DSP program] eetop.cn_Crack_Altera_6.0-9.1

Description: quartus中的DSP Builder6.0到 9.0 的全部破解绝对实用。-quartus 9.0 in all DSP Builder6.0 to break the absolute practical.
Platform: | Size: 296960 | Author: 王小虎 | Hits:

[VHDL-FPGA-Verilog] Quartus-9.0-books

Description: Quartus 9.0 tt_nios2_hardware_tutorial, embeded_handbook, n2cpu_nii72v1_HRDWR_REF, n2cpu_nii72v3_EMBD_PRFR, n2sw_nii72v2_SOFTWR_DEV, ug_nios2_getting_started
Platform: | Size: 8557568 | Author: Vadim | Hits:

[VHDL-FPGA-Verilog] Crack_Altera_6[1][1].0-9.1

Description: quartus版本的破解 从6.1至9.0间所有版本-quartus crack version from 6.1 to 9.0 all versions
Platform: | Size: 138240 | Author: ziluolee | Hits:

[DSP program] Crack_Altera_6.0-9.1

Description: DSP builder6.0-9.0和quartus ii6.0-9.0等版本的破解器，注意运行破解器时最好关闭杀毒软件，否则有可能会出错-DSP builder6.0-9.0 and quartus ii6.0-9.0 and other versions of the cracker, pay attention to when the best off running the cracker antivirus software, or they may be wrong
Platform: | Size: 137216 | Author: | Hits:

[VHDL-FPGA-Verilog] PWM_Module

Description: Very clean design of a PWM module made in structural VHDL. Lower blocks are behavioral.Designed in Quartus 9.0,
Platform: | Size: 1713152 | Author: nada | Hits:

[Other] Quartus--errors-and-worning

Description: Quartus 9.0 常见的一些错误与警告，及一些可用的解决方案，涵盖了几乎大多数人都会遇到的错误与警告~-Quartus 9.0 Some common warning and error description, and some solutions, basically covering errors and warnings that most people will encounter ~
Platform: | Size: 156672 | Author: JX | Hits:

[Develop Tools] Quartus II 9.1 (64-Bit)可用的破解器

Description: 【实例简介】 经过验证的Quartus II 9.1 (64-Bit)可用的破解器 【实例截图】 【核心代码】 QuartusII9.1(64-Bit)可用的破解器 └── Quartus II 9.1 (64-Bit)可用的破解器 └── Quartus91Crack.rar 1 directory, 1 file
Platform: | Size: 1802462 | Author: chenpeishen2012@163.com | Hits:

[VHDL-FPGA-Verilog] multiplier fpga

Description: Multiplication of two numbers from 0 to 9. The first number is displayed on the HEX7 indicator, increases with the KEY3 button, and decreases with the KEY2 button, the second is displayed on the HEX5 indicator, increases with the KEY1 button and decreases with the KEY0 button. The LPM_MULT module is used as a library module. Simulated in Active-HDL Aldec. Project made in Quartus II.
Platform: | Size: 995970 | Author: w3bpunk | Hits:
« 12 3 4 5 6 7 8 9 10 ... 17 »

CodeBus www.codebus.net