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Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114780 |
Author: king.xia |
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Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114688 |
Author: |
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Description: 这一资料详细讲解了如何在quartus中使用modelsim，具有一定的参考价值-This information is detailed account of how to use Quartus modelsim, has a certain reference value
Platform: |
Size: 160768 |
Author: weiwei |
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Description: BJ-EPM240V2实验例程以及说明文档实验之十五Quartus II调用ModelSim仿真实例-BJ-EPM240V2 experimental test routines as well as documentation of the Quartus II 15 ModelSim simulation calls
Platform: |
Size: 421888 |
Author: 王建毅 |
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Description: 通过设计一个简化的计算机模型，培养利用有限状态机的概念设计复杂电路的思维，在设计过程中体会VHDL的RTL风格描述以及EDA工具Quartus的使用方法。同时了解CPU的控制原理与控制过程
通过动脑和动手解决数字逻辑设计中的实际问题，明确，巩固和灵活应用所学的理论知识，提高设计能力和实践操作技能。
-Through the design of a simplified computer models, to cultivate the concept of finite state machine design complex circuit of thinking, experience in the design process, VHDL RTL style description and use of EDA tools Quartus. At the same time to understand the control theory and control process of the CPU through the brains and hands to solve practical problems in digital logic design, clear, consolidate and flexible to apply their theoretical knowledge, improve design capabilities and practical skills.
Platform: |
Size: 371712 |
Author: 伍蔚 |
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Description: FFT 32K点设计实例v1.0.0自述文件
本自述文件包含以下部分：
工具要求
o Quartus II编译
o ModelSim仿真模型
o MATLAB模型(FFT 32K Point Design Example v1.0.0 README File
This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains
information about the design example posted on the Altera Support website:
http://www.altera.com/support/examples/exm-index.html
Ensure that you have read the information on the design example web page
before using the example.
This readme file contains the following sections:
o Package Contents
o Tool Requirements
o Quartus II Compilation
o ModelSim Simulation Models
o MATLAB Models
o Core Directory Names
o Release History
o Design Examples Disclaimer
o Contacting Altera)
Platform: |
Size: 1120256 |
Author: wsf-jv |
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