Search - quartus ii C

[Software Engineering] mycpu

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, such as decoding circuitry. Simulated clock pulse is also given. Has been run through the Quartus II 5.0. Can be addressed to the need to design bus architecture students CPU reference point.
Platform: | Size: 800768 | Author: 陈佳 | Hits:

[Embeded-SCM Develop] NIOS_LED

Description: 完整的Nios 2 演示工程，包括Quartus II 工程和NIOS IDE下的c代码。采用NIOS 2处理器控制LED。已通过实验测试。-Complete Nios 2 demonstration projects, including the Quartus II and NIOS IDE works under the c code. NIOS 2 processor to control the use of LED. Experimental tests have passed.
Platform: | Size: 763904 | Author: M | Hits:

[Other] get_6675_temp_2

Description: MAXII 240 CPLD和6675 开发的0-1023.75度的温度传感数据采集系统，用seg7 LED显示，精度0.25度。探头是K型测温线，Quartus II 6.0调是通过，在cpld开发板上面试验成功-MAXII 240cpld and 0-1023.75 development of 6675 degrees C temperature sensor data acquisition system, using seg7 LED shows that the accuracy of 0.25 degrees. K-type temperature probe is a line, Quartus II 6.0 transfer is approved, the development board cpld successfully tested above. The MAX6675 performs cold-junction compensation and digitizes the signal from a type-K thermocouple. The data is output in a 12-bit resolution, SPI™-compatible, read-only format. This converter resolves temperatures to 0.25°C, allows readings as high as+1024°C, and exhibits thermocouple accuracy of 8LSBs for temperatures ranging from 0°C to+700°C. controller is cpld
Platform: | Size: 464896 | Author: 谭建平 | Hits:

[ARM-PowerPC-ColdFire-MIPS] LED

Description: 在ALTERA的DE 2 开发板上做的一个类似闪烁的彩灯，用了16个LEDR，可以直接下载到板子上运行，基于经典的开发平台Quartus II+SOPC Builder+Nios II IDE 做的，只要看了以后，你就会自己设计各种花样的彩灯闪烁的样子了.所用语言有多种，VHDL,C/C++等-DE 2 in the development of the ALTERA board to do a similar flickering lantern, with a 16 LEDR, can be directly downloaded to the board on the operation of the development platform based on the classic Quartus II+ SOPC Builder+ Nios II IDE to do, just have to look at After, you will design their own patterns of lanterns flicker the same again. There are a variety of language, VHDL, C/C++, etc.
Platform: | Size: 4208640 | Author: liguoyin | Hits:

[VHDL-FPGA-Verilog] sopcIIC

Description: 该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。整个项目是在Quartus II 7.0和nios IDE环境下开发。-This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is written in c language. The project is to complete the project, according to the reference and a higher economic value. The example is a project originally done. The whole project is in the Quartus II 7.0 and the nios IDE development environment.
Platform: | Size: 13532160 | Author: bobo | Hits:

[VHDL-FPGA-Verilog] or1200_wb_ram_gpio_pll

Description: Quartus ii项目，硬件平台为SOPC2000，能实现LED的各种显示控制及按键输入。包括硬件实现的Verilog及软件实现的C实现。SOPC系统的设计在Windows的quaruts ii 8.0上实现，软件部分在Ubuntu上实现。-Quartus ii project, the hardware platform for SOPC2000, to achieve a variety of LED display control and key input. Including Verilog hardware implementation and software implementation of the C implementation. SOPC system design in Windows, to achieve quaruts ii 8.0, software to achieve some of the Ubuntu.
Platform: | Size: 637952 | Author: 陶宇 | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core_latest.tar

Description: IIC IP核，可以直接集成在SOPC中的(⊙o⊙)哦-基于Quartus II 可直接集成到SOPC，自定义II C IP核
Platform: | Size: 4562944 | Author: zy | Hits:

[VHDL-FPGA-Verilog] Chapter-1

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 2048 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-2

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 5120 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-3

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 4096 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-4

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 7168 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-5

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 15360 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-6

Description: 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 3072 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-7

Description: 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 7168 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-8

Description: 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 335872 | Author: shixiaodong | Hits:

[Other Embeded program] MyC2Board_RS232_Test

Description: 这是一个Altera FPGA NIOS II RS232通讯程序。在Quartus II工程中，用Qsys建立了一个NIOS II为核心的CPU系统，并挂接了一个RS232接口。在software目录下，有三个工程，一个是用C++类包装的RS232类的Eclipse工程，一个是不用C++类包装的Eclipse工程，还有一个是用VC++2008编写的RS232测试工程。 VC++2008编写的工程运行在PC机上，与FPGA中的NIOS II通讯。这个实验的主要目的是编写一个通用RS232类，这个类即可以用于NIOS II，又可以用于PC机，是一个可重用的RS232类；我们用这个类开发了不少以PC为控制平台，FPGA为硬件控制器的测试系统。 -This is an Altera FPGA NIOS II RS232 communication project. In the Quartus II project, there is a NIOS II CPU with RS232. In the Software directory, there are 3 projects. First one is an Eclipse Project with C++ RS232 Class. Second one is an Eclipse Project with C RS232.h. Other one is a VC++2008 Project with C++ RS232 Class. The purpose of this project is to write a RS232 Class use on any system needed RS232 communication. The RS232 Class not only use on NIOS II, but also use on PC. We used this RS232 Class on many Test Systems with PC and FPGA
Platform: | Size: 13864960 | Author: li hui xian | Hits:

[matlab] matlab与Quartus II接口

Description: matlab与Quartus II接口 Copyright (c) 2009, Sreeram Mohan All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met
Platform: | Size: 5108 | Author: slaceware@sina.com | Hits:

[VHDL-FPGA-Verilog] EP2C8-2010_FPGA

Description: EP2C208C8 FPGA开发源代码（芯蓝C8板） turn_on_led 点亮LED sw_led 拨动开关控制LED rider_led 跑马灯 water_led 流水灯 key_led_without_debounce 轻触开关控制LED，无按键去抖 key_led_with_debounce 轻触开关控制LED，有按键去抖 seg7x8_dynamic_disp 七段数码管动态显示 matrixKeyboard_seg7 测试矩阵键盘，七段数码管显示 beep_test 滴滴声，测试蜂鸣器 beep_matrixKeyboard 简易不同频率发声器 lcd1602_test 测试LCD1602显示 lcd1602_clock 简易时钟，LCD1602显示 vga_color_slip VGA显示彩条 vga_char VGA显示字符 uart_tx_test 串口发送测试 uart_rx_test 串口接收测试 ps2_keyboard_test PS2键盘测试，LCD1602显示-# Copyright (C) 1991-2009 Altera Corporation # Your use of Altera Corporation s design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. --------------------------------------------------------------------------# # # Quartus II # Version 9.0 Build 132 02/25/2009 SJ Full Version # Date created = 09:05:11 March 14, 2010 # #--------------
Platform: | Size: 3846144 | Author: wqc | Hits:

[Software Engineering] Quartus2_12.0_full_license

Description: Quartus II 12.0 最新license完全破解！找了很多个版本的license综合而成.其他版应该也可以使用. CRC/FIR/FFT/IFFT compiler ,signal tap 等多达102项功能破解. 包括附费才能使用的c语言到硬件加速功能C2H compiler. -Quartus II 12.0 full license
Platform: | Size: 28672 | Author: 刘春焱 | Hits:

[VHDL-FPGA-Verilog] mif_generation

Description: 利用C生成quartus中ROM所需用的mif或者hex文件，以正弦信号为例-Using C to generate .mif for quartus ii
Platform: | Size: 1024 | Author: 里昂 | Hits:

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