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[VHDL-FPGA-Verilog] Quartus2-superLicense

Description: 万能Lisence,本许可适用于各个版本的Quartus-Omnipotent Lisence, this license applies to all versions of the Quartus
Platform: | Size: 19456 | Author: jiangmin | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[Other] Crack_QII90_SP2

Description: Quartus II 9.0 SP2 破解-crack for Quartus II 9.0 SP2
Platform: | Size: 14336 | Author: 胡文静 | Hits:

[Embeded-SCM Develop] fft3

Description: quartus 9.0 中FFT IP核的使用方法附带工程文件和用signaltapII抓到的波形-quartus 9.0 in FFT IP core attached to the use of engineering documents and the use of captured waveform signaltapII
Platform: | Size: 13032448 | Author: hewenlong | Hits:

[VHDL-FPGA-Verilog] learn_dds

Description: 基于quartus ii 9.0的简易dds波形发生器，可以产生正弦，方波，三角波，可变幅，可变频。非常适合学习使用，使用时请按自己的芯片和引脚设置-Quartus ii 9.0 Based on dds simple waveform generator can produce sine, square, triangle wave can be amplitude, frequency can be. Very suitable for learning to use, when used by their chip and pin set
Platform: | Size: 732160 | Author: 陈东旭 | Hits:

[Windows Develop] learn_rom_99multi

Description: 基于quartus ii 9.0的99乘法器，用rom表做成的乘法器可以计算9*9的乘法，并在数码管上显示，使用时请按照自己的芯片和引脚设置。-Quartus ii 9.0 based on 99 multiplier, made by rom multiplier table can calculate the multiplication 9* 9, and in the digital control display, according to their own use when the chip and pin set.
Platform: | Size: 487424 | Author: 陈东旭 | Hits:

[Other] quartus9.1

Description: 9.1版本破解！ 9.1版本破解！ -for quartus 9.1for quartus 9.1for quartus 9.1for quartus 9.1
Platform: | Size: 909312 | Author: yanghaixiang | Hits:

[VHDL-FPGA-Verilog] sdramtEST

Description: sdram动态存储器测试的源文件工程，Quartus II 9.0 (32-Bit)版本。-sdram TEST
Platform: | Size: 3500032 | Author: luyi | Hits:

[VHDL-FPGA-Verilog] sinbo

Description: 基于quartus II的正弦波发生器，可调频率相位，用其时序仿真即可显示，分模块设计的。有sin。mif文件.-Based quartus II of the sine wave generator, adjustable frequency and phase, with the timing simulation can show that sub-module design. A sin. mif file.
Platform: | Size: 995328 | Author: liyu | Hits:

[Other] Crack_Quartus+II+9.1

Description: Its crack file for Altera Quartus 9.1
Platform: | Size: 20480 | Author: Giang | Hits:

[VHDL-FPGA-Verilog] LCD12864

Description: LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
Platform: | Size: 621568 | Author: 王冠 | Hits:

[VHDL-FPGA-Verilog] 2BCD

Description: 二进制转BCD码 verilog hdl Quartus II 9.0sp2 编译通过 所有的文件-Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
Platform: | Size: 286720 | Author: 王冠 | Hits:

[Embeded-SCM Develop] lab1

Description: 本实验主要练习使用Quartus II 9.1软件进行简单的FPGA 的I/O口实验，实验使用的是DE2开发板，使用芯片为EP2C35F672C6。本次实验的重点是掌握Quartus II 进行系统设计的流程、方法及调试技巧，并对DE2开发板的各个引脚的含义及使用有所了解。-This experiment and practice using the Quartus II 9.1 software is a simple FPGA' s I/O port experiments using a DE2 development board, using the chip EP2C35F672C6. The focus of this experiment is to master the Quartus II design flow, methods, and debugging techniques, and each pin DE2 development board understand the meaning and use.
Platform: | Size: 586752 | Author: xjnkasndx | Hits:

[VHDL-FPGA-Verilog] SDRAMPNIOS-II

Description: 带SDRAM的nios II系统，开发环境为Quartus II 9.0 + Nios II 9.0-With the nios II SDRAM system, development environment for the Quartus II 9.0+ Nios II 9.0
Platform: | Size: 7397376 | Author: 张非 | Hits:

[VHDL-FPGA-Verilog] chengfaqi

Description: verilog语言编写的一个乘法器程序，是16位相乘！已通过仿真，用Quartus II 9.1 编写-a multiplier verilog language program, is 16 multiplied by! Through simulation, the Quartus II 9.1 to write
Platform: | Size: 1775616 | Author: mr liu | Hits:

[VHDL-FPGA-Verilog] vga

Description: verilog语言编写的一个vga程序，是vga显示程序，用Quartus II 9.1 编写-a vga verilog language program is a vga display program, the Quartus II 9.1 to write
Platform: | Size: 829440 | Author: mr liu | Hits:

[VHDL-FPGA-Verilog] lcd

Description: verilog语言编写的一个lcd控制程序，是lcd显示程序，用Quartus II 9.1 编写-verilog language lcd control procedures, lcd display program written using the Quartus II 9.1
Platform: | Size: 1114112 | Author: mr liu | Hits:

[GPS develop] Code_NCO.zip

Description: 码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
Platform: | Size: 1024 | Author: cc | Hits:

[VHDL-FPGA-Verilog] CNTlum

Description: 使用Windows7 系统，quartus ii 9.1 软件，Verilog 语言 0到9的计数，并且亮度逐渐增大(count from 0 to 9,and the lum become more and more high)
Platform: | Size: 1354752 | Author: Eris | Hits:

[VHDL-FPGA-Verilog] (笔记)Quartus-II-9.1完全操作教程

Description: Quartus II 的操作指南 新手操作指南 有详细步骤和截屏(a detailed guide of Quartus II)
Platform: | Size: 528384 | Author: miyoujia | Hits:
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