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[VHDL-FPGA-Verilog] shuzhijietiaoqu DL : 0: 基于FPGA的全数字调制解调器设计实例，包含有Matlab程序和Quartus程序-FPGA-based all-digital modem design example, contains the procedures and Quartus program Matlab
Update : 2025-02-17 Size : 641kb Publisher :
[MiddleWare] MIF_create DL : 0: MIF文件生成器用于quartus II等软件的ROM表mif文件生成-MIF file generator quartus II software for the ROM table to generate mif file
Update : 2025-02-17 Size : 216kb Publisher : 高
[VHDL-FPGA-Verilog] ug_lpm_rom DL : 0: quartus rom的生成运用matlab生成.mif或.hex文件载入rom表-quartus rom the use of matlab generated generation. mif or. hex file loading rom Table
Update : 2025-02-17 Size : 805kb Publisher : 王欣欣
[Other] MATLAB_and_FPGA DL : 0: 附录光盘说明本书附赠的光盘包括各章节实例的设计工程与源码，所有工程在下列软件环境下运行通过： ? Windows XP SP2 ? MATLAB ? Altera Quartus II ? synplify8.4 ? modelsim_ae6.1 光盘目录与实例名称的对应关系如下： cht02文件夹中存放的是书中第2章中的例子，读者可以将一些简单例子的代码拷贝到MATLAB命令窗口进行运行，也可以把一些复杂的例子做成一个单独的*.m文件然后运行、调试(要将每行前的“>>”删除)。 cht04文件夹存放的是书中第4章的例子代码。每个例子都建立了一个单独的文件夹，除了存放与例子相关的代码外，还对各个例子建立了Quartus II工程，编制了仿真测试向量，并对例子进行了编译、综合、布局布线和时序仿真。 cht05文件夹中存放的是一个完整的正弦波频率产生的例子，即书中5.4.1节中的代码，读者可以应用这些代码建立自己的项目，按照书中介绍的方法，获得完整的项目设计经验。注意事项：光盘中的源代码为作者编写，并调试通过，有兴趣的读者可以在此基础上进行二次开发，但请不要用作商业用途。 -CD-ROM Appendix Description The book comes with a CD-ROM includes examples of various sections of the design engineering and source code, all works in the following software environment to run through: ? Windows XP SP2 ? MATLAB ? Altera Quartus II ? Synplify8.4 ? Modelsim_ae6.1 CD-ROM directories and examples of correspondence between the names is as follows: cht02 folders stored in the book are Chapter 2 of the examples, readers may be some simple code examples Copy to the MATLAB command window to run, you can put some examples of the complex into a single And the*. m files to run, debug (to each line before the ">>" delete). cht04 folders stored in the book are examples of Chapter 4 code. Examples of each set up a separate folder, In addition to the storage associated with the example code, but also examples of each set up a Quartus II project, the preparation of the simulation test vectors, and examples have been compiled, integrated, p
Update : 2025-02-17 Size : 6.64mb Publisher : 吕成林
[VHDL-FPGA-Verilog] Quartus DL : 0: 1.七段数码管译码器 2.4人表决器 3.4进制加减法计数器~具有进位和借位功能-1. Seven-Segment LED Decoder 2.4 M 3.4 people voting machine counters ~ with addition and subtraction and by-bit binary function
Update : 2025-02-17 Size : 1kb Publisher : 胡志伟
[VHDL-FPGA-Verilog] DE2_SD_Card_Audio(Modified) DL : 0: 在DE2开发板上实现的SD卡mp3音乐播放器。硬件部分用Verilog语言编写，在Quartus上编译；软件部分用C语言编写，在Nios2上编译运行。-DE2 development board in the realization of the SD card mp3 music player. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2.
Update : 2025-02-17 Size : 2.88mb Publisher : 符玉襄
[VHDL-FPGA-Verilog] digital_frequency DL : 0: 用verilog实现数字频率计的设计，具有自动换挡功能，采用t法和m法设计，低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.
Update : 2025-02-17 Size : 481kb Publisher : 孙岩
[VHDL-FPGA-Verilog] m-mtip-10_100_1000_ethermac DL : 1: 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
Update : 2025-02-17 Size : 42kb Publisher : 天一生水
[VHDL-FPGA-Verilog] hm DL : 0: 汉明编码和解码的硬件描述语言（verilog），其被编解码的数据为M序列。建议运行软件为Quartus.-failed to translate
Update : 2025-02-17 Size : 305kb Publisher :
[VHDL-FPGA-Verilog] BPSK DL : 0: 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.BPSK3中程序的目的是：将m序列通过滚降系数为0.3的升余弦滤波系统后的信号采样输出。 3.BPSK5中程序的目的是：将m序列通过滚降系数为0.5的升余弦滤波系统后的信号采样输出。 4.以上两个程序的运行平台为Quartus（verilog语言）。-BPSK modulation is used to design, as follows: 1.matlab.txt the program is under matlab platform. Mat format. Purpose is to output a 64* 4 matrix, each element is an integer between 0 and 255. Matrix of each line is a symbol of four the number of sampling points of the four quantitative value. However, due to the current symbol by raised cosine filtering system, before and after a total of six yards by the combined effect of element, it is shared by the six yards per decision. The 6 symbol is random, may be 0 may be 1 (may be bipolar may be+1-1), so a total of six yards per 2 ^ 6 = 64 kinds of situations, so the resulting matrix 64* 4. Finally, the number of progressive output of the 256. 2.BPSK3 purposes of the procedure is: m sequence of roll-off factor of 0.3 by the raised cosine filter system output after the signal sampling. 3.BPSK5 purposes of the procedure is: m sequence of roll-off factor of 0.5 by the raised cosine filter system output after the signal sampling.
Update : 2025-02-17 Size : 4kb Publisher :
[VHDL-FPGA-Verilog] design217 DL : 0: 在quartus II中实现的一段分频代码，具有很好的使用价值，希望大家能够更好的借鉴。-FW FWKPJF F WJL FW FEL,M FW,M GERWELJ GEW RMGLEJWR4E GER ER FL OFE RGFE GRE GRTE GTRE 4ER OT EWWQO .
Update : 2025-02-17 Size : 297kb Publisher : 李万林
[VHDL-FPGA-Verilog] m_sequence DL : 0: 用verilog语言描述了M序列（伪随机通信）的编码、解码、纠错等功能，本人通过了Quartus II 以及Modelsim的仿真。-Verilog language description of the M sequence (pseudo-random communication) encoding, decoding, error correction, I passed the Quartus II and Modelsim simulation.
Update : 2025-02-17 Size : 6kb Publisher : 周青晖
[VHDL-FPGA-Verilog] frequency-meter DL : 0: 开发环境是quartus ii，是学校的一个FPGA实验，计算一个信号的频率，这个是我做得最好的一个作品，调试成功。压缩包里包含题目要求以及我做好的模块。-Development environment is quartus ii, an FPGA experimental school, calculate the frequency of a signal, this is I' m doing the best work, debugging success. The compression bag module contains the subject of the request, and I do a good job.
Update : 2025-02-17 Size : 36kb Publisher : 尉世乾
[matlab] MATLAB-and-Verilog-codes DL : 0: there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other for four to two bits encoder circuit.
Update : 2025-02-17 Size : 2kb Publisher : YAZEN H
[Other] RISC模型机设计 DL : 0: quartus软件，设计一台RISC模型机，要求具有以下功能：输入包含10个整数（无符号数）的数组M，按从小到大的顺序输出这10个数。
Update : 2016-11-15 Size : 890.1kb Publisher : 810842304@qq.com
[VHDL-FPGA-Verilog] m-Sequence DL : 0: FPGA,verilog,输出M序列，已调试成功，可直接在Quartus上打开。-FPGA, verilog, output M sequence, has been successfully debugged, can be opened directly on the Quartus.
Update : 2025-02-17 Size : 4.88mb Publisher : 秦枫
[Communication-Mobile] 频谱m程序 DL : 0: 根据Quartus导出stp文件导出的txt数据，把txt文档里的无关内容删除，仅保留数据，可使用该m程序，轻松画出频谱图，作为开发人员的测试工具(Export the txt data derived from the STP file according to Quartus, delete the irrelevant content in the txt document, only retain the data, use the M program, and easily draw the spectrogram, as the developer's testing tool)
Update : 2025-02-17 Size : 33kb Publisher : laodajerry