Search - quartus modelsim

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[Other resource] modelsim DL : 0: 这一资料详细讲解了如何在quartus中使用modelsim，具有一定的参考价值
Update : 2008-10-13 Size : 157.13kb Publisher : weiwei
[Other resource] Modelsim DL : 0: 不错的Quartus II 与modelsim结合仿真简介笔记，较为适合初学者，希望对大家有帮助！
Update : 2008-10-13 Size : 1.3mb Publisher : 刘英
[Other] Quartus+II+++ModelSim+SE+++后仿真+++库文件.rar DL : 0: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。
Update : 2009-09-01 Size : 985.47kb Publisher : t613@163.com
[VHDL-FPGA-Verilog] 89_full_adder DL : 0: full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
Update : 2025-02-17 Size : 4kb Publisher : shenyunfei
[VHDL-FPGA-Verilog] altera_ram DL : 0: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Update : 2025-02-17 Size : 176kb Publisher : panyouyu
[VHDL-FPGA-Verilog] AdderEmodelSim DL : 0: altera Quartus II modelSim 自動模擬搭配，內有範例。 (含電路) -altera Quartus II modelSim with automatic simulation, there are examples. (With circuit)
Update : 2025-02-17 Size : 187kb Publisher : 陳小龍
[Software Engineering] modelsim DL : 0: 这一资料详细讲解了如何在quartus中使用modelsim，具有一定的参考价值-This information is detailed account of how to use Quartus modelsim, has a certain reference value
Update : 2025-02-17 Size : 157kb Publisher : weiwei
[File Format] KONAMI DL : 0: 至今还没有弄明白为什么要用ModelSim，因为看波形Quartus II自带的工具就可以了-Has yet to find out why to use ModelSim, because the Quartus II Waveform look built-in tools can be a
Update : 2025-02-17 Size : 1.54mb Publisher : liuyong
[Other] 4_in_1 DL : 0: 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。-Cytech latest quartus8.0 the license, including the Quartus II 8.0, NIOS II 8.0 (in the Quartus II
Update : 2025-02-17 Size : 325kb Publisher : 王网
[VHDL-FPGA-Verilog] Modelsim DL : 0: 不错的Quartus II 与modelsim结合仿真简介笔记，较为适合初学者，希望对大家有帮助！
Update : 2025-02-17 Size : 1.29mb Publisher : 刘英
[VHDL-FPGA-Verilog] Des2Sim DL : 0: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Update : 2025-02-17 Size : 1.86mb Publisher : 黄鹏曾
[VHDL-FPGA-Verilog] Modelsim DL : 0: modelsim 的使用具体方法与步骤以及与Quartus联合仿真-ModelSim the use of specific methods and procedures, as well as a joint simulation with the Quartus
Update : 2025-02-17 Size : 232kb Publisher : 王欣欣
[VHDL-FPGA-Verilog] QuartusIIandModelSim DL : 0: 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform.
Update : 2025-02-17 Size : 271kb Publisher : 朱雯
[VHDL-FPGA-Verilog] Quartus_fft_ip_core DL : 0: Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试)-Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
Update : 2025-02-17 Size : 292kb Publisher : 刘晓彬
[VHDL-FPGA-Verilog] Quartus_II_called_ModelSim_simulation DL : 0: BJ-EPM240V2实验例程以及说明文档实验之十五Quartus II调用ModelSim仿真实例-BJ-EPM240V2 experimental test routines as well as documentation of the Quartus II 15 ModelSim simulation calls
Update : 2025-02-17 Size : 412kb Publisher : 王建毅
[Software Engineering] HuaWei_FPGA_Design DL : 0: 华为FPGA设计流程说明由于目前所用到的FPGA器件以Altera的为主，所以下面的例子也以Altera为例，工具组合为 modelsim + LeonardoSpectrum/FPGACompilerII + Quartus，但原则和方法对于其他厂家和工具也是基本适用的。-Huawei FPGA design flow as a result of the current devices used to Altera' s FPGA-based, so the following examples to Altera for example, tools for modelsim+ LeonardoSpectrum/FPGACompilerII+ Quartus, but the principles and methods and tools for other manufacturers is also basic application.
Update : 2025-02-17 Size : 31kb Publisher : qinzhan
[VHDL-FPGA-Verilog] I2C DL : 0: 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA，一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。仿真工具：modelsim 综合工具：quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Update : 2025-02-17 Size : 8kb Publisher : huangjiaju
[VHDL-FPGA-Verilog] quartus-and-modelsim-for-OFDM DL : 0: 关于quartus与modelsim 仿真-about quartus and modelsim simulator
Update : 2025-02-17 Size : 1.48mb Publisher : donglijun
[VHDL-FPGA-Verilog] Quartus-II-Design-modelsim DL : 0: Update : 2025-02-17 Size : 1.86mb Publisher : adin
[Software Engineering] Quartus_Modelsim_setup DL : 0: communication between quartus II and modelsim altera
Update : 2025-02-17 Size : 359kb Publisher : minou

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