Search - quartus7

[Other] Quartus_II_7.0_decoder

Description: Altera公司的Quartus7.0的lisence 破解程序-Altera's Quartus7.0 the lisence crack procedures
Platform: | Size: 5886 | Author: sylivian | Hits:

[Other resource] osc

Description: 数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过
Platform: | Size: 2243597 | Author: 李星 | Hits:

[Other resource] fftinterface

Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram
Platform: | Size: 4933712 | Author: 李星 | Hits:

[Other resource] coverlater

Description: 本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。
Platform: | Size: 989 | Author: 柯陡 | Hits:

[Other resource] Quartus7.2_crack

Description: qutartusII7.2的破解工具。之不过是在6.0的基础上，但是可以用。
Platform: | Size: 543480 | Author: guobo | Hits:

[Other resource] Altera_Avalon

Description: quartus7.1的avalon总线的测试。
Platform: | Size: 12038 | Author: 雷 | Hits:

[Other resource] svpwm_full_nios

Description: 这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240
Platform: | Size: 12646564 | Author: 汉武帝 | Hits:

[Other] Quartus_II_7.0_decoder

Description: Altera公司的Quartus7.0的lisence 破解程序-Altera's Quartus7.0 the lisence crack procedures
Platform: | Size: 5120 | Author: sylivian | Hits:

[Other] q2_7_license

Description: altera quartus 2 7.0 许可文件-altera quartus 2 7.0 permit documents
Platform: | Size: 6144 | Author: 尤 | Hits:

[VHDL-FPGA-Verilog] Key7.1SP1(b178)

Description: Qutuas II v7.1的key_gen 对sp1无效这就是个v7.1 sp1的key_gen -Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
Platform: | Size: 41984 | Author: 陈勇 | Hits:

[VHDL-FPGA-Verilog] osc

Description: 数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过-Digital Oscilloscope The FPGA realization of VHDL test preparation Quartus7.1
Platform: | Size: 2243584 | Author: 李星 | Hits:

[VHDL-FPGA-Verilog] fftinterface

Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Platform: | Size: 4933632 | Author: 李星 | Hits:

[VHDL-FPGA-Verilog] coverlater

Description: 本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。-This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.
Platform: | Size: 1024 | Author: 柯陡 | Hits:

[VHDL-FPGA-Verilog] Quartus7.2_crack

Description: qutartusII7.2的破解工具。之不过是在6.0的基础上，但是可以用。-qutartusII7.2 the crack tool. It is based on the 6.0, but can be used.
Platform: | Size: 542720 | Author: guobo | Hits:

[VHDL-FPGA-Verilog] Altera_Avalon

Description: quartus7.1的avalon总线的测试。-the avalon bus quartus7.1 testing.
Platform: | Size: 11264 | Author: 雷 | Hits:

[Other] forpof

Description: quartus2 7.1 版本的license,FPGA开发工具的授权文件-quartus2 7.1 version of the license, FPGA development tools authorization documents
Platform: | Size: 347136 | Author: shushu | Hits:

[VHDL-FPGA-Verilog] svpwm_full_nios

Description: 这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240
Platform: | Size: 13167616 | Author: 汉武帝 | Hits:

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[Other] Quartus_II_7.0_decoder

[Other resource] osc

[Other resource] fftinterface

[Other resource] coverlater

[Other resource] Quartus7.2_crack

[Other resource] Altera_Avalon

[Other resource] svpwm_full_nios

[Other] Quartus_II_7.0_decoder

[Other] q2_7_license

[VHDL-FPGA-Verilog] Key7.1SP1(b178)

[VHDL-FPGA-Verilog] osc

[VHDL-FPGA-Verilog] fftinterface

[VHDL-FPGA-Verilog] coverlater

[VHDL-FPGA-Verilog] Quartus7.2_crack

[VHDL-FPGA-Verilog] Altera_Avalon

[Other] forpof

[VHDL-FPGA-Verilog] svpwm_full_nios

[VHDL-FPGA-Verilog] Quartus7.2

[VHDL-FPGA-Verilog] quartusII7.2license(2)

[VHDL-FPGA-Verilog] Quartus7.2andModelSim

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