Search - quartus8.

[Other] 4_in_1

Description: 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。
Platform: | Size: 333553 | Author: 王网 | Hits:

[Other] 4_in_1

Description: 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。-Cytech latest quartus8.0 the license, including the Quartus II 8.0, NIOS II 8.0 (in the Quartus II
Platform: | Size: 332800 | Author: 王网 | Hits:

[VHDL-FPGA-Verilog] crack-81

Description: 最新QuartusII8.1的补丁，安装它的破解器，可以获得长期使用权-QuartusII8.1 the latest patch, install it to break, and access to long-term use rights
Platform: | Size: 14336 | Author: zxl | Hits:

[VHDL-FPGA-Verilog] twice_freqencey

Description: 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
Platform: | Size: 231424 | Author: nikui | Hits:

[VHDL-FPGA-Verilog] fft_VHDL

Description: 使用altra的quartus8.1作为开发环境，用硬件语言VHDL实现了fft的变化-Altra as quartus8.1 use the development environment, language VHDL hardware changes to achieve the fft
Platform: | Size: 71680 | Author: 黄易飞 | Hits:

[VHDL-FPGA-Verilog] shuzi4

Description: 四位数字乘法器，在quartus8.0下仿真时序图 -mult4
Platform: | Size: 175104 | Author: standabc | Hits:

[VHDL-FPGA-Verilog] Crack_QII81_FULL_License

Description: quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
Platform: | Size: 29696 | Author: wcm | Hits:

[VHDL-FPGA-Verilog] 2c8_lcd12864

Description: 用quartus8.1创建的基于ALter公司的EP2C8的12864液晶显示一幅画的完整工程文件。-Quartus8.1 created using the company' s EP2C8 based ALter liquid crystal display a picture of the 12864 complete project file.
Platform: | Size: 151552 | Author: 胡丹 | Hits:

[VHDL-FPGA-Verilog] Quartus8.1_licence

Description: A way to evalulate Quartus 8.1
Platform: | Size: 400384 | Author: efarem | Hits:

[VHDL-FPGA-Verilog] VHDL-djdplj

Description: 基于VHDL语言的十进制等精度频率计的设计，采用VHDL语言，运用自顶向下的设计思想，将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design, the system is divided by function layer hierarchical design method, the use of Quartus8.0 development environment, to achieve a frequency meter design.
Platform: | Size: 228352 | Author: ldd | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-dengjingduc

Description: 本文介绍了基于VHDL语言的十进制等精度频率计的设计，采用VHDL 语言，运用自顶向下的设计思想，将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。 -This article describes the decimal-based VHDL, and other precision frequency meter design, using VHDL language, the use of top-down design, the system is divided by function layer hierarchical design method, the use of Quartus8.0 development environment, implemented frequency meter design.
Platform: | Size: 280576 | Author: 筱诺 | Hits:

[VHDL-FPGA-Verilog] shumaguan

Description: 基于数码管的蛇形灯程序设计，开发环境为quartus8.1，在开发板上实现。-LED lights on the serpentine design, development environment for quartus8.1, in the development of on-board implementation.
Platform: | Size: 2159616 | Author: 李生 | Hits:

[VHDL-FPGA-Verilog] st_1

Description: 12位dac8413驱动 vhdl编写 quartus8.1测试通过-dac8413 vhdl drive
Platform: | Size: 414720 | Author: fafengted | Hits:

[VHDL-FPGA-Verilog] ipcore

Description: quartus8.0的LPM参数化宏模块ipcore应用-quartus8.0 the LPM parameterized macro module ipcore application
Platform: | Size: 819200 | Author: danny | Hits:

[VHDL-FPGA-Verilog] decoder

Description: 基本门电路和译码器试验，含quartus8.0工程，源码，仿真和详细操作步骤，适合初学者上手。-Basic gate circuit and decoder tests, including quartus8.0 engineering, source code, simulation and detailed steps for beginners to get started.
Platform: | Size: 813056 | Author: lifan | Hits:

[VHDL-FPGA-Verilog] uart_receive_send_verilog

Description: 自己写的串口quartus8.0工程，串口收发virilog程序，在EP1C3T144C8芯片验证运行成功，时钟频率50Mhz，波特率115200.-Own write serial quartus8.0-engineering serial transceiver virilog program runs successfully verified, in EP1C3T144C8 chip clock frequency of 50Mhz, baud rate 115200.
Platform: | Size: 502784 | Author: lifan | Hits:

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[Other] 4_in_1

[Other] 4_in_1

[VHDL-FPGA-Verilog] crack-81

[VHDL-FPGA-Verilog] twice_freqencey

[VHDL-FPGA-Verilog] fft_VHDL

[VHDL-FPGA-Verilog] shuzi4

[VHDL-FPGA-Verilog] Crack_QII81_FULL_License

[VHDL-FPGA-Verilog] 2c8_lcd12864

[VHDL-FPGA-Verilog] Quartus8.1_licence

[VHDL-FPGA-Verilog] VHDL-djdplj

[VHDL-FPGA-Verilog] FPGA-VHDL-dengjingduc

[VHDL-FPGA-Verilog] shumaguan

[VHDL-FPGA-Verilog] st_1

[VHDL-FPGA-Verilog] ipcore

[VHDL-FPGA-Verilog] decoder

[VHDL-FPGA-Verilog] uart_receive_send_verilog

[VHDL-FPGA-Verilog] test_access_rot_edit2

[VHDL-FPGA-Verilog] frequency_measure

[VHDL-FPGA-Verilog] dutyfactor

[VHDL-FPGA-Verilog] f_changed_sin_wave

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