Search - quartus8.

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[Other] 4_in_1 DL : 0: 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。
Date : 2008-10-13 Size : 325.74kb User : 王网
[Other] 4_in_1 DL : 0: 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。-Cytech latest quartus8.0 the license, including the Quartus II 8.0, NIOS II 8.0 (in the Quartus II
Date : 2025-07-04 Size : 325kb User : 王网
[VHDL-FPGA-Verilog] crack-81 DL : 0: 最新QuartusII8.1的补丁，安装它的破解器，可以获得长期使用权-QuartusII8.1 the latest patch, install it to break, and access to long-term use rights
Date : 2025-07-04 Size : 14kb User : zxl
[VHDL-FPGA-Verilog] twice_freqencey DL : 0: 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
Date : 2025-07-04 Size : 226kb User : nikui
[VHDL-FPGA-Verilog] fft_VHDL DL : 0: 使用altra的quartus8.1作为开发环境，用硬件语言VHDL实现了fft的变化-Altra as quartus8.1 use the development environment, language VHDL hardware changes to achieve the fft
Date : 2025-07-04 Size : 70kb User : 黄易飞
[VHDL-FPGA-Verilog] shuzi4 DL : 0: 四位数字乘法器，在quartus8.0下仿真时序图 -mult4
Date : 2025-07-04 Size : 171kb User : standabc
[VHDL-FPGA-Verilog] Crack_QII81_FULL_License DL : 0: quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
Date : 2025-07-04 Size : 29kb User : wcm
[VHDL-FPGA-Verilog] 2c8_lcd12864 DL : 0: 用quartus8.1创建的基于ALter公司的EP2C8的12864液晶显示一幅画的完整工程文件。-Quartus8.1 created using the company' s EP2C8 based ALter liquid crystal display a picture of the 12864 complete project file.
Date : 2025-07-04 Size : 148kb User : 胡丹
[VHDL-FPGA-Verilog] Quartus8.1_licence DL : 0: A way to evalulate Quartus 8.1
Date : 2025-07-04 Size : 391kb User : efarem
[VHDL-FPGA-Verilog] VHDL-djdplj DL : 0: 基于VHDL语言的十进制等精度频率计的设计，采用VHDL语言，运用自顶向下的设计思想，将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design, the system is divided by function layer hierarchical design method, the use of Quartus8.0 development environment, to achieve a frequency meter design.
Date : 2025-07-04 Size : 223kb User : ldd
[VHDL-FPGA-Verilog] FPGA-VHDL-dengjingduc DL : 0: 本文介绍了基于VHDL语言的十进制等精度频率计的设计，采用VHDL 语言，运用自顶向下的设计思想，将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。 -This article describes the decimal-based VHDL, and other precision frequency meter design, using VHDL language, the use of top-down design, the system is divided by function layer hierarchical design method, the use of Quartus8.0 development environment, implemented frequency meter design.
Date : 2025-07-04 Size : 274kb User : 筱诺
[VHDL-FPGA-Verilog] shumaguan DL : 0: 基于数码管的蛇形灯程序设计，开发环境为quartus8.1，在开发板上实现。-LED lights on the serpentine design, development environment for quartus8.1, in the development of on-board implementation.
Date : 2025-07-04 Size : 2.06mb User : 李生
[VHDL-FPGA-Verilog] st_1 DL : 0: 12位dac8413驱动 vhdl编写 quartus8.1测试通过-dac8413 vhdl drive
Date : 2025-07-04 Size : 405kb User : fafengted
[VHDL-FPGA-Verilog] ipcore DL : 0: quartus8.0的LPM参数化宏模块ipcore应用-quartus8.0 the LPM parameterized macro module ipcore application
Date : 2025-07-04 Size : 800kb User : danny
[VHDL-FPGA-Verilog] decoder DL : 0: 基本门电路和译码器试验，含quartus8.0工程，源码，仿真和详细操作步骤，适合初学者上手。-Basic gate circuit and decoder tests, including quartus8.0 engineering, source code, simulation and detailed steps for beginners to get started.
Date : 2025-07-04 Size : 794kb User : lifan
[VHDL-FPGA-Verilog] uart_receive_send_verilog DL : 0: 自己写的串口quartus8.0工程，串口收发virilog程序，在EP1C3T144C8芯片验证运行成功，时钟频率50Mhz，波特率115200.-Own write serial quartus8.0-engineering serial transceiver virilog program runs successfully verified, in EP1C3T144C8 chip clock frequency of 50Mhz, baud rate 115200.
Date : 2025-07-04 Size : 491kb User : lifan
[VHDL-FPGA-Verilog] test_access_rot_edit2 DL : 0: This file is VHDL code. sram access code. device name is Atera cyclone2. in quartus8.1 webedition.
Date : 2025-07-04 Size : 505kb User : kimjuhyun
[VHDL-FPGA-Verilog] frequency_measure DL : 0: 简单实现数字频率计，开发环境：Quartus8.0-Simple digital frequency meter development environment: Quartus8.0
Date : 2025-07-04 Size : 1.95mb User : 赵东方
[VHDL-FPGA-Verilog] dutyfactor DL : 0: 可调占空比程序，开发环境：Quartus8.0-Adjustable duty cycle of program development environment: Quartus8.0
Date : 2025-07-04 Size : 393kb User : 赵东方
[VHDL-FPGA-Verilog] f_changed_sin_wave DL : 0: 用RAM实现频率可调正弦波发生器，开发环境：Quartus8.0-To frequency tunable sine wave generator development environment: Quartus8.0 using RAM
Date : 2025-07-04 Size : 1.14mb User : 赵东方

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