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Description: 这是最新版的Quartus9.的破解文件,怎么做我就不说了,里面说的很清楚,我已经尝试,保证能用!希望大家学习愉快!-This is the latest version of Quartus9.' s Crack file, how do I do not say, which says very clearly, I have tried to ensure that can be! Hope that we learn with pleasure!
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Size: 313344 |
Author: 雁过无痕呢 |
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Description: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
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Size: 3072 |
Author: homeuser |
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Description: quartus9.0破解器,能够破解quartus9.0-quartus crack
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Size: 14336 |
Author: |
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Description: 9.1版本破解! 9.1版本破解! -for quartus 9.1for quartus 9.1for quartus 9.1for quartus 9.1
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Size: 909312 |
Author: yanghaixiang |
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Description: 数字电路设计nameseqdet build in Quartus9.1-nameseqdet build in Quartus9.1
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Size: 1144832 |
Author: Smith |
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Description: Verilog实现的Uart模块,在quartus9.1环境下已综合、运行成功。-Verilog implementation Uart module has been integrated in the quartus9.1 environment, run successfully.
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Size: 1024 |
Author: 左左 |
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Description: quartus9.1正式版的破解软件,操作简便-quartus9.1 the official version of the cracked software,
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Size: 1472512 |
Author: sqf |
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Description: 本代码利用SOPC实现走马灯功能,在QUARTUS9.0,NIOSII9.0环境下开发。-Using SOPC implementation of the code features a revolving door in QUARTUS9.0, NIOSII9.0 development environment.
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Size: 12020736 |
Author: fd |
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Description: 用FPGA实现dct变换。verilog语言实现,在quartus9.0中验证,含整个工程-dct transform verilog language in quartus9.0 verify, with the entire project
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Size: 1224704 |
Author: ys |
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Description: IIR二阶节的直接型实现,Quartus9.1编译通过。-Direct form of IIR SOS
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Size: 5120 |
Author: toplure |
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Description: 示波器源程序,由quartus9.1编写,verilog语言支持。采样频率为1M等效采样速率可以到200M-Oscilloscope source code, written by the quartus9.1, verilog language support. Sampling frequency of 1M to 200M equivalent sampling rate can
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Size: 11951104 |
Author: 欧阳锋 |
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Description: 可以用于破解Quartus II 9.0,9.0SP2,9.1。
内部已经有说明文档。-Cracker for Quartus II 9.0,9.0SP2,9.1.
Notice the readme file in it.
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Size: 77824 |
Author: zcxvegeta |
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Description: 流水式BOOTH乘法器,包含整个工程文件,用Quartus9编写打开。为8bit乘以8bit乘法器-Flow BOOTH multiplier, contains the entire project file, open with Quartus9 written. Multiplied for 8bit 8bit multiplier
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Size: 189440 |
Author: 郭里 |
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Description: 基于QUARTUS9.1 的 程序 例程用于 CYCLONE II ep2c5t144 开发板测试-guangyuQUARTUS de licheng yongyuceshi CYCLONE II ep2c5t144 board
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Size: 2023424 |
Author: huguoli |
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Description: cos_table主要应用在GPS接收机中,通过quartus9.1 的编程实现,控制接收的程序,cos_table main application in the GPS receiver, through the programming of the quartus9.1 implementation, control the received program
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Size: 7168 |
Author: cc |
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Description: IIR50Hz数字工频陷波,Altera cyclone2开发板,Quartus9.1软件工程的文件,Verilog HDL代码。-IIR50Hz digital frequency notch, Altera cyclone2 development board, Quartus9.1 project files, Verilog HDL code.
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Size: 3602432 |
Author: jiangph |
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Description: Digital clock using Quartus9.1 platform, using Verilog language, to share to everyone
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Size: 1829888 |
Author: huyunchuan |
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Description: Digital clock using Quartus9.1 platform, using Verilog language, to share to everyone
Platform: |
Size: 2010112 |
Author: huyunchuan |
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Description: quartus9.0 全功能license(quartus9.0 full license)
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Size: 2048 |
Author: CSCSCSCSCS
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Description: vhdl入门实例,一位全加器和一位半加器的quartus9.1程序,可直接运行(VHDL entry examples, a full adder and a half adder quartus9.1 program, can be run directly)
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Size: 2632704 |
Author: 芮芊
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