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[VHDL-FPGA-VerilogQuartus9.0crackfile

Description: 这是最新版的Quartus9.的破解文件,怎么做我就不说了,里面说的很清楚,我已经尝试,保证能用!希望大家学习愉快!-This is the latest version of Quartus9.' s Crack file, how do I do not say, which says very clearly, I have tried to ensure that can be! Hope that we learn with pleasure!
Platform: | Size: 313344 | Author: 雁过无痕呢 | Hits:

[VHDL-FPGA-Verilogoc_i2c_master_top_v92

Description: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Platform: | Size: 3072 | Author: homeuser | Hits:

[VHDL-FPGA-VerilogCrack_QII90

Description: quartus9.0破解器,能够破解quartus9.0-quartus crack
Platform: | Size: 14336 | Author: | Hits:

[Otherquartus9.1

Description: 9.1版本破解! 9.1版本破解! -for quartus 9.1for quartus 9.1for quartus 9.1for quartus 9.1
Platform: | Size: 909312 | Author: yanghaixiang | Hits:

[OtherNameSeqDet

Description: 数字电路设计nameseqdet build in Quartus9.1-nameseqdet build in Quartus9.1
Platform: | Size: 1144832 | Author: Smith | Hits:

[VHDL-FPGA-VerilogWBUart

Description: Verilog实现的Uart模块,在quartus9.1环境下已综合、运行成功。-Verilog implementation Uart module has been integrated in the quartus9.1 environment, run successfully.
Platform: | Size: 1024 | Author: 左左 | Hits:

[VHDL-FPGA-VerilogQuartusP9.1-hack

Description: quartus9.1正式版的破解软件,操作简便-quartus9.1 the official version of the cracked software,
Platform: | Size: 1472512 | Author: sqf | Hits:

[VHDL-FPGA-Verilogquartus

Description: 本代码利用SOPC实现走马灯功能,在QUARTUS9.0,NIOSII9.0环境下开发。-Using SOPC implementation of the code features a revolving door in QUARTUS9.0, NIOSII9.0 development environment.
Platform: | Size: 12020736 | Author: fd | Hits:

[VHDL-FPGA-Verilogdct_verilog

Description: 用FPGA实现dct变换。verilog语言实现,在quartus9.0中验证,含整个工程-dct transform verilog language in quartus9.0 verify, with the entire project
Platform: | Size: 1224704 | Author: ys | Hits:

[VHDL-FPGA-VerilogIIR_2

Description: IIR二阶节的直接型实现,Quartus9.1编译通过。-Direct form of IIR SOS
Platform: | Size: 5120 | Author: toplure | Hits:

[VHDL-FPGA-Verilogf_measure_3

Description: 示波器源程序,由quartus9.1编写,verilog语言支持。采样频率为1M等效采样速率可以到200M-Oscilloscope source code, written by the quartus9.1, verilog language support. Sampling frequency of 1M to 200M equivalent sampling rate can
Platform: | Size: 11951104 | Author: 欧阳锋 | Hits:

[OtherQuatersCrack

Description: 可以用于破解Quartus II 9.0,9.0SP2,9.1。 内部已经有说明文档。-Cracker for Quartus II 9.0,9.0SP2,9.1. Notice the readme file in it.
Platform: | Size: 77824 | Author: zcxvegeta | Hits:

[VHDL-FPGA-Verilogbooth_mul

Description: 流水式BOOTH乘法器,包含整个工程文件,用Quartus9编写打开。为8bit乘以8bit乘法器-Flow BOOTH multiplier, contains the entire project file, open with Quartus9 written. Multiplied for 8bit 8bit multiplier
Platform: | Size: 189440 | Author: 郭里 | Hits:

[Software EngineeringDevelop-a-Verilog-module-for-a-2

Description: 基于QUARTUS9.1 的 程序 例程用于 CYCLONE II ep2c5t144 开发板测试-guangyuQUARTUS de licheng yongyuceshi CYCLONE II ep2c5t144 board
Platform: | Size: 2023424 | Author: huguoli | Hits:

[VHDL-FPGA-Verilogcostable.zip

Description: cos_table主要应用在GPS接收机中,通过quartus9.1 的编程实现,控制接收的程序,cos_table main application in the GPS receiver, through the programming of the quartus9.1 implementation, control the received program
Platform: | Size: 7168 | Author: cc | Hits:

[VHDL-FPGA-Verilogiir_50hz

Description: IIR50Hz数字工频陷波,Altera cyclone2开发板,Quartus9.1软件工程的文件,Verilog HDL代码。-IIR50Hz digital frequency notch, Altera cyclone2 development board, Quartus9.1 project files, Verilog HDL code.
Platform: | Size: 3602432 | Author: jiangph | Hits:

[VHDL-FPGA-VerilogElevator_controller

Description: Digital clock using Quartus9.1 platform, using Verilog language, to share to everyone
Platform: | Size: 1829888 | Author: huyunchuan | Hits:

[VHDL-FPGA-VerilogVerilog_digital_clock

Description: Digital clock using Quartus9.1 platform, using Verilog language, to share to everyone
Platform: | Size: 2010112 | Author: huyunchuan | Hits:

[VHDL-FPGA-Verilogfull_license

Description: quartus9.0 全功能license(quartus9.0 full license)
Platform: | Size: 2048 | Author: CSCSCSCSCS | Hits:

[VHDL-FPGA-Verilogquartuswork

Description: vhdl入门实例,一位全加器和一位半加器的quartus9.1程序,可直接运行(VHDL entry examples, a full adder and a half adder quartus9.1 program, can be run directly)
Platform: | Size: 2632704 | Author: 芮芊 | Hits:
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