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[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[Software Engineering] FPGA_4FFT

Description: 针对高速数字信号处理的要求,提出用FPGA 实现基- 4FFT 算法,并对其整体结构、蝶形单 元进行了分析. 采用蝶算单元输入并行结构和同址运算,能同时提供蝶形运算所需的4 个操作 数,具有最大的数据并行性,能提高处理速度 按照旋转因子存放规则,蝶形运算所需的3 个旋转 因子地址相同,且寻址方式简单 输出采取与输入相似的存储器 运算单元同时采用3 个乘法的 复数运算算法来实现.-In accordance with the requirements of high speed digital signal processing , the algorithmof radix O4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed. With butterfly u2 nit input which is designed by parallel structure and the same address calculation , four operation codes the butterfly unit needs can be provided simultaneously to have the most data parallel and improve the speed of calculation. According to the rotation parameters memory regulation , the addresses of three rotation parame2 ters of butterfly unit are the same with simple style of address generation and similar input and output memo2 ries. The operating unit adopted is implemented by three complex calculation algorithm of multiplication si2 multaneously.
Platform: | Size: 360448 | Author: 王晓 | Hits:

[VHDL-FPGA-Verilog] vhdlfft4

Description: 基4算法的vhdl实现，蝶形变换等的详细设计-Radix-4 algorithm of VHDL realize, butterfly transform the detailed design, etc.
Platform: | Size: 12288 | Author: 邓翔 | Hits:

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

Description: This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
Platform: | Size: 456704 | Author: alex | Hits:

[VHDL-FPGA-Verilog] VLSIFFTRadix2forDSP

Description: VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application
Platform: | Size: 247808 | Author: bonjour | Hits:

[VHDL-FPGA-Verilog] design

Description: The verilog implementation of 8-point FFT in verilog. Radix 2 Decimation in Frequency.
Platform: | Size: 10240 | Author: Hong-soo | Hits:

[VHDL-FPGA-Verilog] fft_hdl

Description: 一个 16点 FFT 用基2蝶形运算单元完成，有测试环境。-16 points FFT with a radix-2 butterfly computation unit is completed and test environment.
Platform: | Size: 21504 | Author: wei | Hits:

[VHDL-FPGA-Verilog] fft_1024_hdl

Description: 一个 1024 点 FFT ， 基 4 蝶形运算架构， 5级流水，乒乓内存，有测试环境。-A 1024-point FFT, Radix-4 butterfly structure operation, five water, ping-pong memory, a test environment.
Platform: | Size: 18432 | Author: wei | Hits:

[VHDL-FPGA-Verilog] fft2

Description: 512点8位基2fft程序。基于 vhdl/verilog。已仿真布线通过。-512 points, eight base 2fft program. Based on vhdl/verilog. Simulation layout has been adopted.
Platform: | Size: 20480 | Author: 包鼎华 | Hits:

[Algorithm] fft

Description: 16 point 4 radix fft vhdl
Platform: | Size: 2048 | Author: gwangja | Hits:

[VHDL-FPGA-Verilog] cfft4

Description: fft radix-4 VHDL for expanding to any fourier transform
Platform: | Size: 1024 | Author: delta | Hits:

[VHDL-FPGA-Verilog] cfft4X12

Description: fft radix-4 for expanding to any fourier transform
Platform: | Size: 1024 | Author: delta | Hits:

[VHDL-FPGA-Verilog] cf_fft

Description: FFT using C and VHDL. can compute upto 1K, 2K and 4K in radix 2.
Platform: | Size: 3318784 | Author: mimi | Hits:

[VHDL-FPGA-Verilog] FFT_Implementation_in_FPGA

Description: This book is ERICSSON documentation "FFT, REALIZATION AND IMPLEMENTATION IN FPGA". Book includes some theoretical information about FFT Radix-2 and Radix-4, and also VHDL and Matlab code.
Platform: | Size: 297984 | Author: Anta | Hits:

[Books] VHDL

Description: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. -A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
Platform: | Size: 7168 | Author: Michael Lee | Hits:

[Software Engineering] radix4

Description: it s a vhdl code for radix 4 algorithm
Platform: | Size: 101376 | Author: lavish | Hits:

[Software Engineering] RADIX_64

Description: radix 64 point fft using vhdl design in fpga
Platform: | Size: 126976 | Author: bowya | Hits:

[VHDL-FPGA-Verilog] 1024FFVHDL

Description: 1024点基2时分FFT快速傅立叶变换(vhdl) -1024-point radix-2 FFT Fast Fourier transform peak (vhdl)
Platform: | Size: 617472 | Author: leo | Hits:

[VHDL-FPGA-Verilog] cFFT

Description: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be different from the standard FFT algorithm. This variation in gain is not important for orthogonal frequency division modulation (OFDM) and demodulation. The gain can be corrected, to that of a conventional FFT, by applying a constant multiplying factor.
Platform: | Size: 183296 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] butt_dit_r2

Description: buuterfly Radix 2 FFT
Platform: | Size: 1024 | Author: Yousri | Hits:
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