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Description: Turbo码编码器时序控制模块,能够对于RAM,ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
Platform: | Size: 1024 | Author: sunhao | Hits:

[VHDL-FPGA-Verilogram255x8

Description: A Basic ram structure with 256 data handling
Platform: | Size: 1024 | Author: Amal | Hits:

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