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[VHDL-FPGA-Verilog] sram

Description: sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
Platform: | Size: 1024 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] RAMtestbench

Description: 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
Platform: | Size: 1024 | Author: 赵国栋 | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] FPGA_Design_Guide_Chapter1_Westor

Description:
Platform: | Size: 2136064 | Author: 陈枫 | Hits:

[VHDL-FPGA-Verilog] jibengongtestbench

Description: testbench的基本写法，双口ram,双端口的编写 -The basic writing testbench, dual-port ram, dual-port the preparation of
Platform: | Size: 11264 | Author: 陈斌 | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
Platform: | Size: 1024 | Author: 易凯 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 单端口RAM，自己写的单端口RAM，同步写入同步读出，包括TESTBENCH和测试模拟文件-RAM
Platform: | Size: 1024 | Author: wang | Hits:

[VHDL-FPGA-Verilog] doublefloat_RAM

Description: 使用verilog编写的一个双浮点RAM，支持对字、字节、半字、双字的读写，包含testbench和wave.do文件-Use verilog to implement a double float RAM, supporting the read and write of halfword,byte,word,double word. It includes the testbench and wave.do
Platform: | Size: 2048 | Author: WYaode | Hits:

[VHDL-FPGA-Verilog] jpeg_hardware.tar

Description: 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Co
Platform: | Size: 868352 | Author: | Hits:

[VHDL-FPGA-Verilog] VeriRISC_CPU_Verilog

Description: Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
Platform: | Size: 9216 | Author: 张昊溢 | Hits:

[VHDL-FPGA-Verilog] 32_by_8_RAM

Description: 32*8 RAM。Verilog实现。包含TB。-32 by 8 RAM. Testbench included.
Platform: | Size: 3072 | Author: 张昊溢 | Hits:

[Other] ram_test

Description: ISE中双端口不同位宽ram的数据存储，包括testbench-veirlog ram FPGA
Platform: | Size: 2639872 | Author: 安娜 | Hits:

[Embeded-SCM Develop] ise_c8051

Description: r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the rom and ram, you can run the c code. Modelsim simulation scripts contained within the project, the work of the internal hardware can be observed when the program is running.
Platform: | Size: 6135808 | Author: woody.wu | Hits:

[VHDL-FPGA-Verilog] syncram

Description: verilog rtl and testbench code for single port sync ram
Platform: | Size: 1024 | Author: murali krishna | Hits:

[VHDL-FPGA-Verilog] RS422_UART

Description: RS422 串口通讯 （包括 testbench，虚拟RAM，数据收发，波特率生成，数据接收抗干扰）-RS422 UART testbench BaudGen
Platform: | Size: 7168 | Author: 李俊 | Hits:

[VHDL-FPGA-Verilog] inout

Description: 用于RAM的测试文件，以及testbench-some RAM testingfiles，and its testbench
Platform: | Size: 6144 | Author: 小胡 | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:

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