Search - ram code

[Communication] code-demo

Description: HM6264Driver_DS HM6264 RAM的读写驱动程序 S480_Manual_C S480的手动播放范例（for SACMV26e.lib） SetIOBit SPCE061A 利用C语言进行软件端口位操作范例 ShowsinTable 简易正弦波发生器方案，同时提供全正数的正弦表 SleepTimerWakeup 定时中断唤醒CPU的范例 UARTDemo 使用UART中断方式进行通讯的范例 UARTDouble UART双机通讯范例，采用中断方式 -HM6264Driver_DS HM6264 RAM read and write drivers for the S480 manual S480_Manual_C broadcast paradigm (for SACMV26e.lib) SetIOBit SPCE061A C language for the use of port-operating software paradigm ShowsinTable simple sine wave generator programs, is to provide the number of regular sine table SleepTimerWakeup CPU interrupt awaken example UARTDemo use UART interrupt communication paradigm UARTDouble Dual UART communications paradigm Interrupt Mode
Platform: | Size: 285696 | Author: 赵孜恺 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[Other Embeded program] fifo-ram

Description: 采用Verilog语言描述的FIFO和双端口RAM源代码。-Verilog language used to describe the FIFO and dual-port RAM source code.
Platform: | Size: 1024 | Author: 蒋大为 | Hits:

[VHDL-FPGA-Verilog] ram

Description: RAM， Random-access memory，Verilog code-RAM, Random-access memory, Verilog code
Platform: | Size: 14336 | Author: leigh lee | Hits:

[Other] ramchoice

Description: 多总线切换的VHDL代码。可用于多RAM的管理。-Multibus VHDL code switching. RAM can be used for multi-management.
Platform: | Size: 1024 | Author: 祝箭 | Hits:

[Mathimatics-Numerical algorithms] PID-c-source-code

Description: 在使用单片机作为控制cpu时，请稍作简化，具体的PID参数必须由具体对象通过实验确定。由于单片机的处理速度和ram资源的限制，一般不采用浮点数运算，而将所有参数全部用整数，运算到最后再除以一个2的N次方数据（相当于移位），作类似定点数运算，可大大提高运算速度，根据控制精度的不同要求，当精度要求很高时，注意保留移位引起的“余数”，做好余数补偿。这个程序只是一般常用pid算法的基本架构，没有包含输入输出处理部分。-In the use of single-chip microcomputer as the control cpu, please make some simplification, the specific PID parameters must be determined through experiments at specific audiences. As the single-chip processing speed and ram resource constraints, generally do not use floating-point, and will use all parameters of all integers, computing the final 2 and then divided by a N-th power of data (equivalent to shift), similar fixed-point computation can be greatly enhanced speed of operation, according to the different requirements of control precision, when high precision, the attention to retain the shift caused by the balance , do a good job in the balance of compensation. This procedure is commonly used algorithm pid basic structure does not contain input and output part of treatment.
Platform: | Size: 1024 | Author: 王强 | Hits:

[Other Embeded program] code.bundle.lpc23xx.lpc24xx.uvision

Description: 代码是关于LPC2468 外设源代码，其涵盖USB主从模式，和语音处理代码-Code is the source code on the LPC2468 peripherals, and its cover USB master and slave mode, and voice processing code
Platform: | Size: 1340416 | Author: 邹奇章 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: 同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用-Synchronous Dynamic RAM control circuit VHDL source code, in the SOC development can be applied directly
Platform: | Size: 90112 | Author: 26 | Hits:

[VHDL-FPGA-Verilog] ram

Description: ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
Platform: | Size: 1920000 | Author: mamou | Hits:

[VHDL-FPGA-Verilog] ram32b

Description: VHDL code for 32 byte RAM
Platform: | Size: 1024 | Author: Davood | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental requirements. Suitable for beginners learning to use.
Platform: | Size: 9216 | Author: 赵剑平 | Hits:

[VHDL-FPGA-Verilog] CODE

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram verilog
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ram

Description: 用FPGA做的RAM，源码，调试通过，有工程-FPGA to do with RAM, source code, debugging through, there are works
Platform: | Size: 452608 | Author: 马泽龙 | Hits:

[Windows Develop] RAM

Description: Code for designing 16 bit RAM
Platform: | Size: 9216 | Author: Magic | Hits:

[VHDL-FPGA-Verilog] RAM

Description: Ram with 8 bits implemented in vhdl verilog code
Platform: | Size: 3072 | Author: guilherme | Hits:

[VHDL-FPGA-Verilog] RAM

Description: ram code in VHDL with its test code
Platform: | Size: 110592 | Author: sab | Hits:

[Internet-Network] slave-ram-verilog

Description: ram代码用verilog写的，有文字说明-verilog code of ram
Platform: | Size: 33792 | Author: 张明 | Hits:

[VHDL-FPGA-Verilog] ram-rom-VerilogHDL

Description: 利用Verilog编写的各种RAM ROM的代码以及他们的测试模块-Prepared using a variety of RAM ROM Verilog code and their test module
Platform: | Size: 5120 | Author: 王体奎 | Hits:

[VHDL-FPGA-Verilog] ram

Description: verilog 编写的ram代码，开发环境为quartus-ram write verilog code development environment for quartus
Platform: | Size: 2053120 | Author: li | Hits:

[VHDL-FPGA-Verilog] ram

Description: hi this is ram code in vhdl
Platform: | Size: 8192 | Author: mani | Hits:

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[Communication] code-demo

[VHDL-FPGA-Verilog] ram

[Other Embeded program] fifo-ram

[VHDL-FPGA-Verilog] ram

[Other] ramchoice

[Mathimatics-Numerical algorithms] PID-c-source-code

[Other Embeded program] code.bundle.lpc23xx.lpc24xx.uvision

[VHDL-FPGA-Verilog] sdram_ctrl.tar

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] ram32b

[VHDL-FPGA-Verilog] RAM

[VHDL-FPGA-Verilog] CODE

[ARM-PowerPC-ColdFire-MIPS] ram

[Windows Develop] RAM

[VHDL-FPGA-Verilog] RAM

[VHDL-FPGA-Verilog] RAM

[Internet-Network] slave-ram-verilog

[VHDL-FPGA-Verilog] ram-rom-VerilogHDL

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] ram

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