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[Windows Develop] ram

Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Platform: | Size: 1024 | Author: 杨艳 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Platform: | Size: 776192 | Author: 汪旭 | Hits:

[VHDL-FPGA-Verilog] distributed_ram

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 12288 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] dpram_fpga

Description: 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
Platform: | Size: 2831360 | Author: 李伟 | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[Embeded-SCM Develop] dualportRAM

Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Platform: | Size: 90112 | Author: 王雪松 | Hits:

[Streaming Mpeg4] bit_intealeaver1

Description: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
Platform: | Size: 1024 | Author: wenjuner | Hits:

[VHDL-FPGA-Verilog] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码-On the dual-port RAM in Verilog HDL source
Platform: | Size: 3072 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] 62256

Description: EPM1270和ram62256的verilog接口程序，用QuartusII编译
Platform: | Size: 323584 | Author: 汉武帝 | Hits:

[Other Embeded program] SRAMCotroller

Description: 一个SRAM控制器的IP核，很不错，有兴趣的朋友可以下去-An SRAM controller IP core, very good friends who are interested can go on
Platform: | Size: 322560 | Author: liufanyu | Hits:

[VHDL-FPGA-Verilog] SRAM

Description:
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] sram_control

Description: verilog编写fpga与片外SRAM通信模块-Verilog FPGA with the preparation of SRAM chip communication module
Platform: | Size: 418816 | Author: 宇天 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 基于Verilog语言编写的各种只读存储器rom和随机存储器ram-Verilog language based on a variety of read-only memory rom and random access memory ram
Platform: | Size: 704512 | Author: 李辽原 | Hits:

[VHDL-FPGA-Verilog] lpm_ram

Description: altera LPM_RAM的使用,有简单的程式和模拟结论.大家写的时候可以参考.-altera LPM_RAM the use of a simple programming and simulation findings. we can refer to when writing.
Platform: | Size: 1024 | Author: tupeng | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

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