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[
VHDL-FPGA-Verilog
]
dual_RAM
Description:
vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
Platform:
|
Size:
1024
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Author:
易凯
|
Hits:
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Search - ram verilog test_bench