Description: 1.高精度数字秒表（0.01秒的vhdl语言实现）
2.具有定时，暂停，按键随机存储，翻页回放功能；
3.对30M时钟分频产生显示扫描时钟
4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。
5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design) Platform: |
Size: 1995 |
Author:方周 |
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Description: 1.高精度数字秒表（0.01秒的vhdl语言实现）
2.具有定时，暂停，按键随机存储，翻页回放功能；
3.对30M时钟分频产生显示扫描时钟
4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。
5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design) Platform: |
Size: 2048 |
Author:方周 |
Hits:
Search - random scan vhdl