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[VHDL-FPGA-Verilog] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309248 | Author: czy | Hits:

[File Format] designforvideobasedonSDRAM

Description: 在信息处理中，特别是实时视频图像处理中，通常都要对实现视频图像进行处理，而这首先必须设计大容量的存储器，同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点，但因SDRAM的控制结构复杂，常用的方法是设计SDRAM通用控制器，这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此，笔者在研究有关文献的基础上，根据具体情况提出一种独特的方法，实现了对SDRAM的控制，并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转，截取、平移等实时处理。-In information processing, especially real-time video image processing usually have to deal with video images, which must first be designed large-capacity memory, synchronous dynamic random access memory SDRAM Although there are low cost, large capacity, etc., but SDRAM control structure of the complex, commonly used method is to design generic SDRAM controller, which makes a lot of people had to abandon the use of SDRAM and the use of expensive SRAM. To this end, the authors examine the literature based on the specific situation in a unique way to realize the control of SDRAM, and control data through the use of FPGA to realize the order of access to digital video image rotation, interception, translation, such as real-time processing.
Platform: | Size: 137216 | Author: 赵明玺 | Hits:

[Special Effects] the.implement.of.image.pretreatment.algorithm.in.t

Description: 现场可编程逻辑门阵列在实时数字图像处理中的应用-Field-programmable gate array logic in real-time digital image processing
Platform: | Size: 159744 | Author: 刘文娟 | Hits:

[VHDL-FPGA-Verilog] asdd

Description: 论文基于FPGA的高速实时FFT处理器设计，给出了详细的设计流程！-Thesis of high-speed FPGA-based real-time FFT processor design, detailed design gives the flow!
Platform: | Size: 157696 | Author: 邓振淼 | Hits:

[VHDL-FPGA-Verilog] baseonFPGA

Description: 实时电话计费系统是企业、事业单位信息管理的一个重要组成部分。介绍了一种用FPGA 器件实现电话计费系统 的方法, 并给出了设计框图和详细设计过程, 设计采用Verilog_HDL 硬件语言。-Real-time telephone billing system is the enterprise information management institutions as an important component. Introduction of a FPGA device using telephone billing system methods, and gives the design diagram and detailed design process, design hardware Verilog_HDL language.
Platform: | Size: 531456 | Author: daifuxin | Hits:

[VHDL-FPGA-Verilog] UP3_RTC_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒，具有闹钟，整点报时，时间可重新设置等功能，在LCD1602上显示。绝对推荐，比网上其他类似代码功能要全而且经过验证。最关键的是该代码是直接通过I2C总线来获取UP3开发板上的实时时钟芯片的时间的,当然也可以通过I2C对时钟芯片进行设置.-In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified. Most crucial point is that the code is directly through the I2C bus to obtain the UP3 development board real time clock chip time, of course, can also I2C clock chip on the set.
Platform: | Size: 1367040 | Author: kehan | Hits:

[VHDL-FPGA-Verilog] SRAM-PINGPANG

Description: 超声视频图像需要实时地采集并在处理后在显示器上重建，图像存储器就必须不断地写入数据，同时又要不断地从存储器读出数据送往后端处理和显示[11]。为了满足这种要求，可以在采集系统中设置2片容量一样的SRAM，通过乒乓读写机制来管理。任何时刻，只能有1片SRAM处于写状态，同时也只有1片SRAM处于读状态。工作期间，2片SRAM都处于读写状态轮流转换的过程，转换的过程相同，但是状态错开，从而保证数据能连续地写人和读出祯存.-Real-time ultrasound video images need to collect and deal with the reconstruction after the display, image memory must be continually write data, while at the same time continuously sent from the memory读出数据back-end processing and display [11]. To meet this requirement, you can set up collection system capacity of two different SRAM, read and write through the ping-pong mechanisms to manage. At any time, can only have a SRAM in write state, but also the only one at a time the state of SRAM. Work, two SRAM read and write are in the process of converting a state of rotation, the conversion process of the same, but the state staggered to ensure that data can be continuously written and read out Qizhen depositors.
Platform: | Size: 1024 | Author: smj1980 | Hits:

[Special Effects] multilevel_filter

Description: 完整的多级滤波图像处理算法，利用FPGA实现，利用硬件结构实现算法能够满足苛刻的实时性要求。-Complete multi-level filtering image processing algorithms using FPGA realization algorithm using hardware structure able to meet the demanding requirements of real-time.
Platform: | Size: 588800 | Author: 朱磊 | Hits:

[VHDL-FPGA-Verilog] scaler

Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Platform: | Size: 9216 | Author: wgy | Hits:

[Firewall-Security] FPGAFirewall

Description: 本系统由服务器软件控制平台和fpga硬件处理系统组成，其中fpga硬件处理系统是整个系统的核心部分。系统管理员通过服务器的软件控制平台可以对fpga硬件处理系统进行即时的配置，fpga硬件处理系统按照系统管理员的配置进行工作，并会在检测到异常情况或者检测到用户敏感的流量或者数据包的时候通知服务器，服务器会向管理员发送通知。管理员可以在服务器软件平台上做进一步的分析处理。-The control system consists of server software platform and FPGA hardware processing system, of which FPGA hardware processing system is the core of the whole system. System administrator through the server software control platform FPGA hardware can perform real-time processing system configuration, fpga hardware processing system in accordance with the system administrator s configuration, and will be detected or the detection of anomalies to the user-sensitive traffic or packet when the notification server, the server will send a notification to the administrator. An administrator can in the server software platform for further analytical processing.
Platform: | Size: 6212608 | Author: 李佳琦 | Hits:

[VHDL-FPGA-Verilog] DS1307_LCD

Description: 通过IIC总线读写实时时钟DS1307，并把时、分、秒显示在12864液晶屏上，用的CycloneII EP2C8，Quartus环境-Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
Platform: | Size: 1311744 | Author: iversn | Hits:

[Special Effects] Read

Description: 这是一个有关实时模拟和数字图像处理的fpga程序-This is a real-time analog and digital image processing procedures for the FPGA
Platform: | Size: 1024 | Author: cjgqf | Hits:

[VC/MFC] HandelC

Description: Handel-C语言的学习文档。Handel-C语言由C/C++演化而来，可以自动实现C到VHDL、C到Verilog、C到EDIF等转换。在DK环境中，DK+Handel-C工具能直接把基于C语言的设计转变为优化的HDL(可以实现：C到VHDL、C到Verilog、C到EDIF等的自动生成)， 进而通过FPGA实现，从而保证了各种复杂的高难算法在工程应用的实时性。-Handel-C language documentation. Handel-C language by C/C++ Evolved, you can automatically C to VHDL, C to Verilog, C, etc. to convert Edif. In DK environment, DK+ Handel-C tools can be directly to the C language-based design into optimized HDL (can be achieved: C to VHDL, C to Verilog, C, etc. to Edif automatically generated), then through the FPGA to achieve, thus ensuring a variety of complex algorithms in difficult real-time engineering applications.
Platform: | Size: 1439744 | Author: 杜杰 | Hits:

[Special Effects] s_filter

Description: fpga实现图象滤波，实时的实现对输入图象的形态学滤波-FPGA realization of image filtering, real-time realization of the input images of morphological filtering
Platform: | Size: 1024 | Author: vincent zhen | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[VHDL-FPGA-Verilog] jiaotongdeng

Description: 1). 用红、绿、黄三色发光二极管作信号灯。主干道为东西向，有红、绿、黄三个灯；支干道为南北向，也有红、绿、黄三个灯。红灯亮禁止通行；绿灯亮允许通行；黄灯亮则给行驶中的车辆有时间停靠到禁行线之外。 2).由于主干道车辆较多而支干道车辆较少，所以主干道绿灯时间较长。当主干道允许通行亮绿灯时，支干道亮红灯。而支干道允许通行亮绿灯时，主干道亮红灯，两者交替重复。主干道每次放行50秒，支干道每次放行30秒。 在每次由亮绿灯变成亮红灯的转换过程中间，需要亮5秒的黄灯作为过渡，以使行驶中的车辆有时间停靠到禁行线以外。 3). 能实现正常的、即时显示功能。用DE2上的四个七段数码管作为倒计时显示器。分别显示东西、南北方向的红灯、绿灯、黄灯时间。 4).能实现特殊状态的功能显示。设S为特殊状态的传感器信号，当Ｓ=1时，进入特殊状态。当Ｓ=0时，退出特殊状态。按S后，能实现特殊状态功能： （1）显示器闪烁； （2）计数器停止计数并保持在原来的数据； （3）东西、南北路口均显示红灯状态； （4）特殊状态结束后，能继续对时间进行计数。 5).能实现总体清零功能。按下R后，系统实现总清零，计数器由初始状态开始计数，对应状态的指示灯亮。 -1). With red, green, yellow three-color light-emitting diodes for lights. For the east-west trunk road, has red, green, yellow three lights support for the north-south trunk road, there are red, green, yellow three lights. Red light curfew green permit passage yellow light is to the moving vehicles have the time of call to cut outside the lane. 2). Because of the trunk road vehicles more vehicles and less trunk extension, so a longer green time of a main road. When the main road access permit a green light when the trunk road red sticks. Permit access roads and support a green light when the trunk road red, the two alternating repetition. Allowed 50 seconds for each trunk, branch trunk release each 30 seconds. At each green light into red by the conversion process between the need for five seconds of yellow light as a transitional measure to enable the moving vehicles have the time of call to ban outside lane. 3). To achieve a normal, real-time display. Using DE2 four seventh
Platform: | Size: 2048 | Author: 靓仔 | Hits:

[SCM] DS18B20

Description: 基于单片机的DS18B20温度采集系统 实时温度采集 具有报警功能-DS18B20 temperature based on single-chip real-time acquisition system with alarm function of temperature acquisition
Platform: | Size: 151552 | Author: zhouhongxi | Hits:

[Windows Develop] vclock

Description: developing the real time clock using vhdl
Platform: | Size: 4096 | Author: ravi | Hits:

[VHDL-FPGA-Verilog] FPGA_Based_Real-time_Adaptive_Filtering_for_Space

Description: FPGA Based Real-time Adaptive Filtering for Space Applications
Platform: | Size: 314368 | Author: asia | Hits:

[Other] a2

Description: 用MATLAB设计及FPGA实现IIR滤波器的方法 摘要 本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波 器，其阶数低，实时响应快，适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法，对于 四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。-Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.
Platform: | Size: 2021376 | Author: sfef | Hits:
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