Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time. Platform: |
Size: 9216 |
Author:wgy |
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Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future. Platform: |
Size: 81920 |
Author:雷志 |
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Description: ds32c35是dalas生产的实时时钟（RTC）芯片，本程序（在EP2C8Q208C8N上调试通过）在FPGA上构建I2C接口于此时钟芯片通信。可以在LED上动态实时显示时间。利用本程序也可以改编成高精度实时时间测量的程序-ds32c35 is produced by dalas real-time clock (RTC) chip, this program (in the EP2C8Q208C8N debugging via) in the FPGA built this clock chip I2C interface to communicate. LED dynamically in real-time display of time. Using this procedure can also be adapted into a high-precision real time measurement procedures Platform: |
Size: 3898368 |
Author:mn |
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Description: 该数字钟，采用VHDL语言编写，具有即时，跑表，调时，调分，闹铃等功能，另外还可以增加一些功能，例如正点报时等-The digital clock, using VHDL language, with real-time, PaoBiao, adjustable, adjustable, alarm functions, also can add some functions, such as punctual Platform: |
Size: 1327104 |
Author:fushibin |
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