Search - reed solomon encoder vhdl

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[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder DL : 1: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Update : 2025-02-17 Size : 75kb Publisher : 王文
[Software Engineering] rsenc DL : 0: this the code for reed solomon encoder of type 7,3. this is the main module program.-this is the code for reed solomon encoder of type 7,3. this is the main module program.
Update : 2025-02-17 Size : 1kb Publisher : alok
[Software Engineering] mult2 DL : 0: this the multiplier 2 module for the reed solomon encoder-this is the multiplier 2 module for the reed solomon encoder
Update : 2025-02-17 Size : 1kb Publisher : alok
[Software Engineering] mult4 DL : 0: this the multiplier 4 module for the reed solomon encoder-this is the multiplier 4 module for the reed solomon encoder
Update : 2025-02-17 Size : 1kb Publisher : alok
[VHDL-FPGA-Verilog] RS DL : 0: reed selemon encoder vhdl code
Update : 2025-02-17 Size : 76kb Publisher : mohamed saad
[Communication] RS_Encoder DL : 0: its a reed solomon encoder-its a reed solomon encoder.....
Update : 2025-02-17 Size : 121kb Publisher : haroon
[Other] rsencoder_latest.tar DL : 0: reed solomon encoder (255,239) verilog source code
Update : 2025-02-17 Size : 4kb Publisher : 梅国强
[VHDL-FPGA-Verilog] rsvhdl_255_239 DL : 0: a VHDL implementation of 255_239 reed solomon encoder.
Update : 2025-02-17 Size : 3kb Publisher : saad
[Program doc] RS3123 DL : 0: Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its random and unexpected error has a strong error correction capabilities, widely used in digital video broadcasting (DVB) systems and other digital communications. Gives a GF (25) Domains RS (31, 23) algorithm of the encoder is introduced with a Field Programmable Gate Array (FPGA) RS encoder to achieve the principles and processes, and providing a circuit and simulation of the output waveform.
Update : 2025-02-17 Size : 352kb Publisher : 王彬
[VHDL-FPGA-Verilog] RS_DesignNote DL : 0: Reed-solomon decoder, encoder design note
Update : 2025-02-17 Size : 883kb Publisher : Seok Hoon Shin
[VHDL-FPGA-Verilog] rsencoder_latest.tar DL : 0: Reed Solomon Encoder
Update : 2025-02-17 Size : 3kb Publisher : aprsc7