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[Other resources3c44b0_exampie

Description: 创维特的s3c44b0 ARM开发板的触摸屏,串口,RTC的学习的例子-Skyworth Reed's s3c44b0 ARM development boards touch screen, serial, RTC examples of learning
Platform: | Size: 9927 | Author: 李 庆坤 | Hits:

[ARM-PowerPC-ColdFire-MIPSs3c44b0_exampie

Description: 创维特的s3c44b0 ARM开发板的触摸屏,串口,RTC的学习的例子-Skyworth Reed's s3c44b0 ARM development boards touch screen, serial, RTC examples of learning
Platform: | Size: 131072 | Author: 李 庆坤 | Hits:

[CommunicationRS_BCH

Description: Reed Solomon and BCH Encoder
Platform: | Size: 2048 | Author: sshain | Hits:

[Program docLDPCtutorial

Description: Low-density parity-check (LDPC) codes are a class of linear block LDPC codes. The name comes from the characteristic of their parity-check matrix which contains only a few 1’s in comparison to the amount of 0’s. Their main advantage is that they provide a performance which is very close to the capacity for a lot of different channels and linear time complex algorithms for decoding. Furthermore are they suited for implementations that make heavy use of parallelism. They were first introduced by Gallager in his PhD thesis in 1960. Gallager, But due to the computational effort in implementing coder and en- 1960 coder for such codes and the introduction of Reed-Solomon codes, they were mostly ignored until about ten years ago
Platform: | Size: 121856 | Author: mike zhou | Hits:

[SCMFull_parallel_architecture_for_turbo_decoding_of_

Description: A full-parallel architecture for turbo decoding, which achieves ultrahigh data rates when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed-Solomon component codes. The major advantage of our architecture is that it enables the memory blocks between all half-iterations to be removed. Moreover, the latency of the turbo decoder is strongly reduced. The proposed architecture opens the way to numerous applications such as optical transmission and data storage. In particular, the block turbo decoding architecture can support optical transmission at data rates above 10 Gbit=s.
Platform: | Size: 110592 | Author: cordic | Hits:

[Windows DevelopRSCode_papers

Description: Reed-Solomen码的四篇简单论文,对初学者理解RS码很有帮助。来源为知网。-Four Papers About R-S Code, helpful to new comers.Come from CNKI
Platform: | Size: 507904 | Author: zcxvegeta | Hits:

[Linux-UnixJerasure-1.2

Description: Jerasure 纠错码代码库,有Reed-Solomon、Cauchy Reed-Solomon等纠错码的开源实现-Jerasure- A C/C++ Library for a Variety of Reed-Solomon and RAID-6 Erasure Coding Techniques. Copright (C) 2007 James S. Plank
Platform: | Size: 148480 | Author: 李顶 | Hits:

[matlabperformance_nalysis_of_a_link-16_compatible

Description: JTIDS是16号数据链的通道系统,本文主要是对在脉冲干扰的情况下16号链的波形性能分析!-The Link-16 is the tactical data link utilized by the Joint Tactical Information Distribution Syste (JTIDS). The JTIDS system is important due to its wide use by U.S. armed forces, NATO, and other allied militaries. Link-16 is a hybrid frequency-hopped/direct sequence spread spectrum system that utilizes minimum-shift keying (MSK) to modulate the chips, cyclical code-shift keying (CCSK) to modulate the 32-chip symbols, and a (31, 15) Reed Solomon (RS) code with hard decision decoding (UDD) for forward error correction (FEC).
Platform: | Size: 1615872 | Author: 严鹏涛 | Hits:

[assembly languagebluespec-reedsolomon_latest.tar

Description: Reed Solomon decoder implemented in VHDL/Verilog. Includes ASM s
Platform: | Size: 33792 | Author: ahmed | Hits:

[VHDL-FPGA-Verilogug_rsii

Description: Reed-Solomon II MegaCore Function user guide,altera的RS II编解码的宏功能模块的用户手册,是RS的升级版的IP,但大体使用一样。-Reed-Solomon II MegaCore Function user guide, altera s RS II codec macro function module user manual is an upgraded version of the RS s IP, but generally use the same.
Platform: | Size: 401408 | Author: wang | Hits:

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