Search - register file vhdl

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[Communication-Mobile] iic_vhdl DL : 0: iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
Date : 2008-10-13 Size : 869.13kb User : benny
[GIS program] register DL : 0: 32×32的寄存器堆，它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成，最低层次的模块是D触发器，中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器，顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法，先用行为建模方法建立低层模块，然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.
Date : 2025-07-13 Size : 4kb User : 甜
[MacOS develop] REG32 DL : 0: 32位寄存器的VHDL的原代码下载,COOLCOOLCOOL-32-bit register of the original VHDL code download, COOLCOOLCOOL
Date : 2025-07-13 Size : 3kb User : LIU
[Communication-Mobile] iic_vhdl DL : 0: iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist -IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
Date : 2025-07-13 Size : 869kb User : benny
[Other] MANIK DL : 0: MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).-MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).
Date : 2025-07-13 Size : 3.24mb User : hfayed
[matlab] coasess.tar DL : 0: register file in vhdl and alu
Date : 2025-07-13 Size : 6kb User : afzal74
[VHDL-FPGA-Verilog] finalcoursework DL : 0: 用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
Date : 2025-07-13 Size : 42kb User : 三木
[Windows Develop] LFSR DL : 0: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Date : 2025-07-13 Size : 850kb User : 风影
[Other] viterbi213 DL : 0: 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
Date : 2025-07-13 Size : 2.54mb User : jenny
[VHDL-FPGA-Verilog] verilog DL : 0: 文件包含了寄存器，移位寄存器，可能计数器，计数器等用VHDL实现的功能模块。-File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
Date : 2025-07-13 Size : 4kb User : 朱向南
[VHDL-FPGA-Verilog] code DL : 0: register file using verilog
Date : 2025-07-13 Size : 4kb User : tran
[VHDL-FPGA-Verilog] I2C_control DL : 0: Xilinx提供的I2C控制器代码,Master/Slave全功能- Readme File for I2C Customer Pack Created: 7/8/99 ALS Revised: 11/4/99 ALS ******************************************************************************************************************************************** ******************************************************************************************************************************************** File Contents ******************************************************************************************************************************************** This zip file contains the following folders: \doc -- Document for the CoolRunner I2C Controller. \exemplar -- Exemplar synthesis files. This design was synthesized using Exemplar and the resulting EDIF file imported into XPLA Professional V3.22 \vhdl_source -- Source VHDL files: i2c.vhd - top level file i2c_control.vhd - control function for the I2C master/slave shift.vhd - shift register uc_interface.vhd- uC interface f
Date : 2025-07-13 Size : 147kb User : leon
[VHDL-FPGA-Verilog] I2C_register DL : 0: ov7670的寄存器赋初值文件，用verilogHDL编写，设定为rgb格式，640*480大小。-ov7670 register initial value file, with verilogHDL write, set to rgb format, 640* 480 size.
Date : 2025-07-13 Size : 3kb User :
[VHDL-FPGA-Verilog] servomat DL : 0: antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados-antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados
Date : 2025-07-13 Size : 1.01mb User : Jorge
[VHDL-FPGA-Verilog] Register.vhd DL : 0: This file is an asynchronous vhdl Register. It registers the input vector into the output vector when the Enable variable is high.
Date : 2025-07-13 Size : 1kb User : keklaquoi