Description: This a simple vhdl code that perform division using the non restoring algorithm which is often handy-This is a simple vhdl code that perform division using the non restoring algorithm which is often handy Platform: |
Size: 1024 |
Author:mma32 |
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Description: Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register is set to zero. In the second and third stages, s1 and s2, the actual serial division takes place. In the fourth step, s3, quotient and remainder are transferred to the output registers. Nominator and quotient are assumed to be 8 bits wide, while denominator and remainder are 6-bit values. Platform: |
Size: 229376 |
Author:hooman hematkhah |
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