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[VHDL-FPGA-VerilogEdition

Description: VHDL可重用英文书,书中有许多对VHDL可重用的具体介绍,是一般的相关书籍所没有的.-VHDL reusable English book has a lot of reusable VHDL specific introduction is generally not related books.
Platform: | Size: 4564992 | Author: 徐民 | Hits:

[VHDL-FPGA-VerilogReuse-Methodology-Manual-Third-Edition

Description: 进行SOC/IP 设计以及可重用设计的宝典书籍!是synopsys的一位牛牛写的! 主要以mentor和synopssy的设计工具为流程,讲述了SOC/IP可重用设计,验证设计的基本方法。 -For SOC/IP design and reusable design book books! A synopsys Niuniu is written! To mentor and synopssy the main design tools for the process, about the SOC/IP reusable design, the basic method to verify the design.
Platform: | Size: 4564992 | Author: yuhl | Hits:

[OtherBook

Description: Reuse Methodology Manual for System-on-a-Chip Designs. 3rd Edition * – by Keating and Pierre Bricaud. Springer.-Reuse Methodology Manual for System-on-a-Chip Designs. 3rd Edition*- by Keating and Pierre Bricaud. Springer.
Platform: | Size: 10028032 | Author: anthonykang | Hits:

[VHDL-FPGA-VerilogReuse.Methodology.Manual.3rd.Edition

Description: Synopsys公司推出的可重用设计方法学,是RTL设计的重要参考准则-a typical book about writing RTL code
Platform: | Size: 4564992 | Author: tim | Hits:

[OtherReuse-Methodology-Manual-V3

Description: 清晰版!!SOC/IP设计以及可重用设计的宝典! 主要以mentor和synopssy的设计工具为流程,讲述了SOC/IP可重用设计,验证设计的基本方法。-Book for SOC/IP design and reusable design, written by a synopsys expert. Taking mentor and synopssy EDA tools as example, introduced SOC/IP reusable design and basic verification method.
Platform: | Size: 4564992 | Author: chip123 | Hits:

[Other(Kluwer)-Reuse-Methodology-Manual-for-System-on-a

Description: (Kluwer) Reuse Methodology Manual for System-on-a-Chip Designs (3rd Ed.)
Platform: | Size: 4563968 | Author: hossam_fadeel | Hits:

[Software Engineeringeetop.cn_Reuse.Methodology.Manual.3rd.Edition.pdf

Description: reuse methodology manual for verification engineer
Platform: | Size: 4708352 | Author: manikandan | Hits:

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