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[VHDL-FPGA-Verilog] risc cpu

Description: 一个很好的16位cpu ip内核，用quartus写的
Platform: | Size: 5888 | Author: kingkoyan | Hits:

[Embeded-SCM Develop] freerisc8_11

Description: 8位RISC　CPU的VERILOG编程　SOURCECODE-8 RISC CPU VERILOG programs SOURCECODE
Platform: | Size: 275456 | Author: zfhustb | Hits:

[VHDL-FPGA-Verilog] 靳远－源程序

Description: 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
Platform: | Size: 443392 | Author: core_design | Hits:

[ARM-PowerPC-ColdFire-MIPS] ethernet_verilog

Description: 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Platform: | Size: 78848 | Author: 张念华 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44032 | Author: 施向东 | Hits:

[Other] cpu的VERILOG描述

Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Platform: | Size: 369664 | Author: 陈俊 | Hits:

[ARM-PowerPC-ColdFire-MIPS] embedded_risc

Description: 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
Platform: | Size: 128000 | Author: 箫勇天 | Hits:

[VHDL-FPGA-Verilog] RISC

Description: hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
Platform: | Size: 128000 | Author: 12 | Hits:

[VHDL-FPGA-Verilog] 16_risc_cpu

Description: 一个支持精简指令的16位的risc cpu，可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
Platform: | Size: 163840 | Author: 董 | Hits:

[ARM-PowerPC-ColdFire-MIPS] cpu

Description: 精简指令cpu，用verilog编写，详细的教程-RISC cpu, using Verilog prepared and detailed tutorial
Platform: | Size: 215040 | Author: 郑欲 | Hits:

[ARM-PowerPC-ColdFire-MIPS] RISC_Core.ZIP

Description: 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
Platform: | Size: 340992 | Author: jinzhoulang | Hits:

[VHDL-FPGA-Verilog] alu

Description: 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
Platform: | Size: 2048 | Author: 李斌 | Hits:

[VHDL-FPGA-Verilog] ARelativelySimpleRISCCPU

Description: A Relatively Simple RISC CPU 设计源码并附详细的说明文档。可以ModelSim进行仿真，并可以用synplify进行综合。-A Relatively Simple RISC CPU design source with detailed documentation. ModelSim simulation can be carried out, and they can Synplify synthesis.
Platform: | Size: 224256 | Author: hulin | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure
Platform: | Size: 574464 | Author: 毋杰 | Hits:

[Other] RiscCpu

Description: Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
Platform: | Size: 9216 | Author: sss | Hits:

[VHDL-FPGA-Verilog] 32bit_RISC_CPU

Description: 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
Platform: | Size: 2444288 | Author: zys | Hits:

[Windows Develop] RISC_8

Description: 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。-Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
Platform: | Size: 173056 | Author: WangYong | Hits:

[Other] Jh_cpu

Description: Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
Platform: | Size: 52224 | Author: ananliu1 | Hits:

[VHDL-FPGA-Verilog] risc

Description: 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
Platform: | Size: 132096 | Author: 徐明 | Hits:

[VHDL-FPGA-Verilog] 8bitRISCCPU

Description: 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
Platform: | Size: 816128 | Author: dyfdown | Hits:
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