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Description: lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习-LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
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Size: 1024 |
Author: 李允 |
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Description: VHDL code for linear prediction filter based on RLS (recursive least square).
Filter order is set to 4, bit precision set to 12 bits for input and output. Signals are complex signals.
Platform: |
Size: 5120 |
Author: 徐滨 |
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