Search - root VHDL

[Other resource] vhdl平方根

Description: 计算某数的平方根，VHDL语言，使用简单-calculate the square root of a number, VHDL, use simple
Platform: | Size: 40483 | Author: wl | Hits:

[Other resource] arith_lib_cadence

Description: Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
Platform: | Size: 82707 | Author: 喻袁洲 | Hits:

[VHDL-FPGA-Verilog] vhdl平方根

Description: 计算某数的平方根，VHDL语言，使用简单-calculate the square root of a number, VHDL, use simple
Platform: | Size: 39936 | Author: wl | Hits:

[VHDL-FPGA-Verilog] arith_lib_cadence

[Data structs] treeandpicture

Description: 利用邻接矩阵的图广度优先遍历算法, 利用子指针数组的普通树前根遍历算法-The use of adjacency matrix of the graph breadth-first traversal algorithm, using sub-array pointer before the root of the general tree traversal algorithm
Platform: | Size: 11264 | Author: 左 | Hits:

[VHDL-FPGA-Verilog] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15360 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: verilog 硬件平方根算法采用与笔算平方根一样的算法-Verilog hardware and written calculation algorithm uses the square root of the square root of the same algorithm
Platform: | Size: 17408 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] pre_norm_sqrt

Description: 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
Platform: | Size: 2048 | Author: zhshup | Hits:

[Algorithm] cordic

Description: cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.-cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.
Platform: | Size: 2048 | Author: waqas | Hits:

[Software Engineering] CombSquareRoot

Description:
Platform: | Size: 1024 | Author: Sriram | Hits:

[Other] sqrt_01

Description:
Platform: | Size: 1024 | Author: DK | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: This zip file contains the verilog source code for square root calculation and its test bench
Platform: | Size: 2048 | Author: Jaganathan | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算-Square root of the tree-type divider-type device to achieve VERILOG
Platform: | Size: 1024 | Author: 神气 | Hits:

[VHDL-FPGA-Verilog] fast_antilog_latest.tar

Description: Anti-Logarithm (square-root), base-2, single-cycle
Platform: | Size: 1024 | Author: aliakbar | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: 实现任意位数的开方算法，但是不是浮点的算法，-Square root algorithm for arbitrary digit, but not floating-point algorithm, thanks
Platform: | Size: 1024 | Author: lty | Hits:

[VHDL-FPGA-Verilog] A-VHDL-Function-for-finding-SQUARE-ROOT

Description: vhdl coding for square root-vhdl coding for square root...
Platform: | Size: 3072 | Author: a.deivaseelan | Hits:

[VHDL-FPGA-Verilog] infrared-transfer-of-VHDL

Description: 使用硬件描述语言 VHDL 编程：红外线传输系统包括发送方和接收两端，都可以单独进行初始化清零处理。在可以设置准备发送的 8bits 8bits8bits 的数据信息，连同一个偶校验位起发送。接受端收到的数据信息，连同一个偶校验位起发送。接受端收到 8bits的数据信息和一位偶校验后，显示接收到并根判定的数据信息和一位偶校验后，显示接收到并根判定的数据信息和一位偶校验后，判定收到的信息是否出错。-Infrared transmission system including the sender and receiver at both ends, can be used alone to initialize cleared processing. Can be set ready to send the 8bits 8bits8bits of the data, together with an even parity bit from the send. Accept the client receives data sent together with an even parity bit since. The receiving end receives the 8bits of data information and an even parity, displays the received data and the root to determine the information and an even parity received and the root to determine the data and an even parity information received to determine whether an error.
Platform: | Size: 2048 | Author: 东方不败 | Hits:

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[Other resource] vhdl平方根

[Other resource] arith_lib_cadence

[VHDL-FPGA-Verilog] vhdl平方根

[VHDL-FPGA-Verilog] arith_lib_cadence

[Data structs] treeandpicture

[VHDL-FPGA-Verilog] alu-div

[VHDL-FPGA-Verilog] sqrt

[VHDL-FPGA-Verilog] pre_norm_sqrt

[Algorithm] cordic

[Software Engineering] CombSquareRoot

[Other] sqrt_01

[VHDL-FPGA-Verilog] sqrt

[VHDL-FPGA-Verilog] sqrt

[VHDL-FPGA-Verilog] fast_antilog_latest.tar

[VHDL-FPGA-Verilog] sqrt

[VHDL-FPGA-Verilog] A-VHDL-Function-for-finding-SQUARE-ROOT

[VHDL-FPGA-Verilog] infrared-transfer-of-VHDL

[VHDL-FPGA-Verilog] 33-square-root

[VHDL-FPGA-Verilog] Square-Root

[Other] vhdl-ALU-floating-point-single-precision

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