Search - rs encoder and decoder

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[Communication] reed-solomon DL : 2: Simulate, by using c++ ,a communication system consists of binary source, RS(7,3,5)/RS(128,122,7) encoder, BPSK modulator, AWGN channel, coherent demodulator, RS(7,3,5)/RS(128,122,7) BM decoder and sink。-Simulate, by using c, a communication system consists of binary source, RS (7,3,5) / RS (128,122,7) encoder, BPSK modulator, AWGN channel, coherent demodulator, RS (7,3,5 ) / RS (128,122,7) BM decoder and sink.
Update : 2008-10-13 Size : 12.17kb Publisher : 徐鹏
[ELanguage] rs-codec-8-4 DL : 0: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien - search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data - rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Update : 2008-10-13 Size : 43.86kb Publisher : zs8292
[Other resource] RS(32to28)encoderanddecoder DL : 0: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Update : 2008-10-13 Size : 75.54kb Publisher : 王文
[Communication] reed-solomon DL : 0: Simulate, by using c++ ,a communication system consists of binary source, RS(7,3,5)/RS(128,122,7) encoder, BPSK modulator, AWGN channel, coherent demodulator, RS(7,3,5)/RS(128,122,7) BM decoder and sink。-Simulate, by using c, a communication system consists of binary source, RS (7,3,5)/RS (128,122,7) encoder, BPSK modulator, AWGN channel, coherent demodulator, RS (7,3,5 )/RS (128,122,7) BM decoder and sink.
Update : 2025-02-17 Size : 12kb Publisher : 徐鹏
[ELanguage] rs-codec-8-4 DL : 0: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Update : 2025-02-17 Size : 44kb Publisher : zs8292
[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder DL : 1: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Update : 2025-02-17 Size : 75kb Publisher : 王文
[VC/MFC] RScoderdecoder DL : 1: 应用C语言实现RS（255，223）编码器和译码器-Application of C language to achieve RS (255,223) encoder and decoder
Update : 2025-02-17 Size : 50kb Publisher : 吉林思伟
[VHDL-FPGA-Verilog] rs-codec-8-16 DL : 1: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Update : 2025-02-17 Size : 27kb Publisher : 饶进平
[Program doc] RS DL : 0: RS（Reed Solomon）编码器、译码器设计实例-RS (Reed Solomon) encoder and decoder design example
Update : 2025-02-17 Size : 43kb Publisher : ou
[Program doc] rs_enc_dec DL : 0: RS编译码的C程序，用的是很经典的BM算法，已在VC上调试通过-rs encoder and decoder program
Update : 2025-02-17 Size : 7kb Publisher : songbing
[matlab] RS_Code DL : 0: RS编译码的Matlab程序，与陈文礼的《RS纠错编码原理及其实现方法》配套，已调试通过。-RS encoder and decoder ,matlab program
Update : 2025-02-17 Size : 909kb Publisher : songbing
[AI-NN-PR] Rscodes DL : 0: Simulate, by using c, a communication system consists of binary source, RS (7,3,5)/RS (128,122,7) encoder, BPSK modulator, AWGN channel, coherent demodulator, RS (7,3,5 )/RS (128,122,7) BM decoder and sink.
Update : 2025-02-17 Size : 2kb Publisher : ytrwr
[Program doc] rs73 DL : 0: RS（7，3）编解码,采用IBM译码算法，此算法简单易懂，易于用硬件实现-RS encoder and decoder
Update : 2025-02-17 Size : 1kb Publisher : helloman
[VHDL-FPGA-Verilog] ug_rs-compiler DL : 0: altera RS编译码器datasheet-the datasheet of the rs encoder and decoder of altera
Update : 2025-02-17 Size : 404kb Publisher : tangmin
[Other] rs_encoder_decoder DL : 0: RS编解码源程序，有详细的VERILOG程序，用于纠错-RS encoder and decoder
Update : 2025-02-17 Size : 32kb Publisher : williamyang
[Communication] rs DL : 0: reed solomon码是信息理论中信道编码的一种，简称RS码，我上传的用C来仿真实现reed solomon的编码与解码-Reed-Solomon encoder and decoder functions
Update : 2025-02-17 Size : 3kb Publisher : zhangtong
[VHDL-FPGA-Verilog] RS DL : 0: 通过verilog hdl语言实现RS编码器与译码器的设计-Verilog hdl language through the RS encoder and decoder design
Update : 2025-02-17 Size : 26kb Publisher : 李永超
[File Format] rs DL : 0: 基于fpga的rs码编码器与译码器的设计与实现-Design and implementation of rs code encoder and decoder based on fpga
Update : 2025-02-17 Size : 7kb Publisher : 路人甲
[VHDL-FPGA-Verilog] top_rs DL : 0: 利用Xilinx ise的IP CORE写的（255,223）编译码的程序(The use of Xilinx ISE IP CORE written (255223) encoding and decoding procedures)
Update : 2025-02-17 Size : 1kb Publisher : 魏小爱
[Other] rs encoder and decoder DL : 0: 实现了RS编码的详细的功能，附有程序解释。(Realized the detailed function of RS code, with a program explanation.)
Update : 2025-02-17 Size : 4kb Publisher : LSA奥