Search - rs-232 vhdl

Search - rs-232 vhdl - List

[Other resource] S3Demo DL : 0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Update : 2008-10-13 Size : 714.42kb Publisher : Roy Hsu
[Other resource] uart_transmitter DL : 0: Very good info. for RS-232 transmitter VHDL code .
Update : 2008-10-13 Size : 1.13kb Publisher : wan mi
[Other resource] uart_receiver DL : 0: Very good info. for RS-232 receive VHDL code .
Update : 2008-10-13 Size : 1.41kb Publisher : wan mi
[Other resource] ECHO_DE2 DL : 0: Very good info. for RS-232 echo VHDL code .
Update : 2008-10-13 Size : 2.03kb Publisher : wan mi
[VHDL-FPGA-Verilog] RS232-for-vdhl DL : 0: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Update : 2025-02-17 Size : 158kb Publisher : lq
[VHDL-FPGA-Verilog] USBXilinx DL : 0: 实现了串行通信接口的全部功能，符合RS-232-C标准的完整UART模块源代码，中文注解，清晰易懂，经过严格仿真测试，绝对好用。-a serial communication interface of all functions, with RS-232-C standard UART modules complete source code, Chinese notes, lucid, after a rigorous simulation tests, absolutely useful.
Update : 2025-02-17 Size : 452kb Publisher : 张海
[VHDL-FPGA-Verilog] S3Demo DL : 0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Update : 2025-02-17 Size : 714kb Publisher : Roy Hsu
[Communication] URAT DL : 0: 最常见的rs232通信的vhdl实现，经过实际使用验证-The most common communication RS232 VHDL realize, through actual use of authentication
Update : 2025-02-17 Size : 32kb Publisher : 江泽民
[VHDL-FPGA-Verilog] uart_transmitter DL : 0: Very good info. for RS-232 transmitter VHDL code .
Update : 2025-02-17 Size : 1kb Publisher : wan mi
[VHDL-FPGA-Verilog] uart_receiver DL : 0: Very good info. for RS-232 receive VHDL code .
Update : 2025-02-17 Size : 1kb Publisher : wan mi
[VHDL-FPGA-Verilog] RS232 DL : 0: 基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using
Update : 2025-02-17 Size : 16kb Publisher : 陈泽涛
[SCM] ps2_rs232 DL : 0: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）；并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位。 -Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Update : 2025-02-17 Size : 192kb Publisher : yuan
[VHDL-FPGA-Verilog] RS232 DL : 0: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）；并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Update : 2025-02-17 Size : 713kb Publisher : 李华
[VHDL-FPGA-Verilog] rs232_receiver DL : 0: VHDL implementation for an RS-232 receiver system.
Update : 2025-02-17 Size : 1kb Publisher : mert
[VHDL-FPGA-Verilog] RS-232sender DL : 0: 一个串口RS-232 发送模块。基于VHDL语言。-A serial RS-232 send module. Based on the VHDL language.
Update : 2025-02-17 Size : 9kb Publisher : 李超
[Communication-Mobile] RS_Verilog DL : 0: RS码的FPGA实现，verilog语言形式，好参考资料-FPGA realization of RS code, verilog language form, a good reference
Update : 2025-02-17 Size : 99kb Publisher : 张洪
[VHDL-FPGA-Verilog] 232 DL : 0: 实现PS/2接口与RS-232接口的数据传输，可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。-The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received characters.
Update : 2025-02-17 Size : 15kb Publisher : 包宰
[Program doc] IO DL : 0: serial io for rs 232 communication
Update : 2025-02-17 Size : 879kb Publisher : prakash
[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte DL : 0: 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场合，因此可以达到资源利用的最大化。-According to the characteristics of the UART and the portability advantage of FPGA designs，this paper puts forward an embedded UART design method based on FPGA chips．The design method includes description form of FSM and design approach of Top-Down．It’S good to take advantage of VHDL to program the slave module and top module of UART，and then integrate them into the interior of FPGA chip．In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable．
Update : 2025-02-17 Size : 4.84mb Publisher : mabeibei
[VHDL-FPGA-Verilog] 28538604-Spartan-3E-MATLAB-Interface-Documentatio DL : 0: Documentation VHDL communication RS-232 with the spartan 3
Update : 2025-02-17 Size : 306kb Publisher : JT_LADINO

« 12 »