Search - rs232.vhd

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] RS232

Description: xilinx Sparten3E 串行通信及lcd字符显示-xilinx Sparten3E characters serial communication and lcd display
Platform: | Size: 2048 | Author: ronghy | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[VHDL-FPGA-Verilog] uart.vhd

Description: this modul is serial send & resive for RS232
Platform: | Size: 1024 | Author: rez | Hits:

[VHDL-FPGA-Verilog] DataCntrl

Description: 系统由 DataCntrl.vhd 和RS232RefComp.vhd 模块构成。该模块能和PC 机的RS232 终端（比如PC 机上的串口调试工具程序）以波特率9600 通信。-System consists of DataCntrl.vhd and RS232RefComp.vhd module. The module can and PC-RS232 terminal (such as PC, the serial debugging utility) to 9600 baud communication.
Platform: | Size: 2048 | Author: | Hits:

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[VHDL-FPGA-Verilog] vhdl-2

[VHDL-FPGA-Verilog] RS232

[VHDL-FPGA-Verilog] Rs232sourcecode

[VHDL-FPGA-Verilog] uart.vhd

[VHDL-FPGA-Verilog] DataCntrl

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