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[Other] RTLCodingStyleGoldBook_Coding_Guidelines

Description: RTL代码的编写规范的黄金教程,内容非常齐全,从编写规范,测试规范都有详细说明.Winbond Electronics Corp.出版-RTL code regulating the preparation of the Golden Guide, and the content is very complete, from the preparation of standardized, standardized tests have details. Winbond Electronics Corp.. Publishing
Platform: | Size: 479232 | Author: 张华 | Hits:

[Other] Cummings

Description: Clifford E. Cummings经典论文合集，用于ASIC数字设计．-Clifford E. Cummings Collection classic papers for digital ASIC design.
Platform: | Size: 2028544 | Author: 李无名 | Hits:

[GPS develop] FPGAdatatransport

Description: 本文设计的FPGA模块需要对GPS、便携打印机和串口数据进行处理，将详细介绍如何设计FPGA和不同外设之间的数据传输。同时，在RTL编码中，编写使综合与布局布线效果更佳的代码。-In this paper, the design of FPGA modules need for GPS, portable printers, and serial data processing, will be details on how to design FPGA and data transfer between peripherals. At the same time, RTL coding, synthesis and preparation to make better placement and routing code.
Platform: | Size: 11264 | Author: zhanyi | Hits:

[VHDL-FPGA-Verilog] Principles_of_Verifiable_RTL_Design

Description:
Platform: | Size: 1211392 | Author: 杨力 | Hits:

[VHDL-FPGA-Verilog] RTL

Description:
Platform: | Size: 91136 | Author: Dee | Hits:

[Other] RTLHardwareDesignUsingVHDL

Description: Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains -Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains
Platform: | Size: 28478464 | Author: chane | Hits:

[Other] yuqix_datum

Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。 debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考 RTL Coding and Optimization Guide for use with Design Compiler.pdf 数提讲座（1）.wmv 数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。 ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。 基于DDR SDRAM控制时序分析的模型.pdf 全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。 数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真. -i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference. debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference RTL Coding and Optimization Guide for use with Design Compiler.pdf Mention the number of lectures (1). Wmv Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look. ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Platform: | Size: 20989952 | Author: 喻琪 | Hits:

[Books] A_RTL_of_punture_convolution

Description: 一篇很好的 关于删余卷积编码的RTL实现 文中细致的讲解了删余卷积的FPGA实现 对学习仿真和实现的朋友很有用处-I deleted a good convolutional coding on the RTL implementation of the detailed explanations of the text deleted convolution of the FPGA implementation and realization of simulation for learning is very useful friends
Platform: | Size: 337920 | Author: linziy | Hits:

[VHDL-FPGA-Verilog] Altera-Recommended-HDL-Coding-Style

Description: Altera 推荐的HDL编码风格，在学习HDL的时候比较重要，另外对HDL到RTL的映射有一定的帮助。-Altera Recommended HDL Coding Style
Platform: | Size: 238592 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: LCD1602 Verilog 代码实现。包括数据读写，地址读写，初始化。支持4位总线格式。注意:此程序已经在ML506板子上验证过。本人花了好几天调试，开发出来的。值得推荐。-Verilog coding for LCD1602 display
Platform: | Size: 20480 | Author: liangyao | Hits:

[VHDL-FPGA-Verilog] aes_verilog

Description: A RTL verilog coding for the project AES, which is a cryptography based concepts
Platform: | Size: 7396352 | Author: siva | Hits:

[Other] coding-style

Description: QA培训资料,一、 RTL CODE 规范-QA training materials, a, RTL CODE specification
Platform: | Size: 17408 | Author: haifeng | Hits:

[VHDL-FPGA-Verilog] aFifo.vhd.txt

Description: Async. FIFO for rtl coding and simulation
Platform: | Size: 2048 | Author: akurnya | Hits:

[File Format] verilog-coding-rules

Description: Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
Platform: | Size: 172032 | Author: | Hits:

[Other] synthesis_techniques

Description: 综合大规模的ASIC设计对很多设计团队都是挑战，本书专注于前端的设计决策和使用的方法。它包括RTL编码与综合研究，被用来确定最佳的逻辑设计，速度快，面积小，采用自下而上的合成过程自动化的脚本等等。-Synthesizing large multi-million gate designs is a design task that challenges the design team on many fronts, and this user paper focuses on the design decisions and methodology used by a front-end design team. It includes RTL coding and synthesis studies which can be used to determine the best logic design for fast, area efficient synthesis, scripts used to automate the bottom-up synthesis process。
Platform: | Size: 200704 | Author: chip123 | Hits:

[Other] interleave

Description: 使用xilinx13.1编译通过的块交织编码，能够生成RTL图和technology schemtic图-Block using the xilinx13.1 compiled through intertwined coding can generate RTL diagram, and technology schemtic of Figure
Platform: | Size: 605184 | Author: 李刚 | Hits:

[Industry research] RTL-coding-guidelines

Description: RTL coding guidelines Offer a collection of coding rules and guidelines. Make HDL Codes readable, modifiable, and reusable. Achieve optimal results in synthesis and simulation.
Platform: | Size: 416768 | Author: yosso | Hits:

[MPI] pipe_mul

Description: 移位加乘法器的实现；移位加乘法器的流水线结构的实现。代码清晰明了。-multiply verilog RTL；pipelin multiply verilog RTL；good coding stytle
Platform: | Size: 2048 | Author: mayunli | Hits:

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