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[VHDL-FPGA-Verilog] ata.tar DL : 0: 使用verilog和VHDL两种硬件描述语言实现了一个ATA硬盘控制器，包括源代码、测试仿真文件和说明文档-The use of two types of Verilog and VHDL hardware description language to achieve an ATA hard drive controller, including source code, testing, simulation files and documentation
Update : 2025-02-17 Size : 816kb Publisher : qinlei
[VHDL-FPGA-Verilog] sata_device_model DL : 0: sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
Update : 2025-02-17 Size : 16.61mb Publisher : 磊
[VHDL-FPGA-Verilog] aips7108.tar DL : 0: SATA 仿真模型 SATA 仿真模型-Simulation Model SATA SATA SATA simulation model simulation model
Update : 2025-02-17 Size : 16.83mb Publisher : 罗宇平