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Description: 一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现
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Size: 3112 |
Author: xl |
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Description: 一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming
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Size: 3072 |
Author: fredyu |
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Description: sdh 标准 itu G0709.rar-SDH standard itu G0709.rar
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Size: 149504 |
Author: 陈小冲 |
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Description: <SDH原理培训手册>对SDH学习的初学者帮助很大！对SDH原理及实现讲的非常详细！也很容易拢懂！还有课后习题与参考答案！对知识有很好的巩固作用！最后祝各位学习愉快！-<SDH原理培训手册> Of SDH of the study is very helpful for beginners! Principle and Realization of SDH speak in great detail! Together is also very easy to understand! There are after-school exercise and reference the answer! Of knowledge has a very good role in the consolidation! Finally wish you all a happy studying!
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Size: 406528 |
Author: yangyin |
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Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
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Size: 6144 |
Author: 韩冰 |
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Description: SDH基础知识，非常适合于初学者学习通信的基础知识-Basic knowledge of SDH, very suitable for beginners to learn the basic knowledge of communication
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Size: 3231744 |
Author: wuchao |
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Description: 他是一个SDH上行代码，有八个模块组成的，能够传输以太网的数据 -He is an SDH uplink code, there is composed of eight modules, Ethernet can transmit data
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Size: 6144 |
Author: 丁勇良 |
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Description: 对vga接口做了详细的介绍，并且有一
·三段式Verilog的IDE程序，但只有DMA
·电子密码锁，基于fpga实现，密码正
·IIR、FIR、FFT各模块程序设计例程，
·基于逻辑工具的以太网开发，基于逻
·自己写的一个测温元件（ds18b20）的
·光纤通信中的SDH数据帧解析及提取的
·VHDL Programming by Example（McGr
·这是CAN总线控制器的IP核，源码是由
·FPGA设计的SDRAM控制器，有仿真代码
·xilinx fpga 下的IDE控制器原代码,
·用verilog写的，基于查表法实现的LO
·精通verilog HDL语言编- up:in STD_LOGIC
down:in STD_LOGIC
run_stop:in STD_LOGIC
wai_t: in std_logic_vector(2 downto 0)
lift:in std_logic_vector(2 downto 0)
ladd: out std_logic_vector(1 downto 0)
)
end control
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Size: 18683904 |
Author: liuzhou |
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Description: SDH的有关介绍，包括：
SDH介绍.pdf，
SDH传输时隙环回定位故障.pdf，
SDH传输网的时钟优化.pdf。-SDH relevant, including: SDH introduced. Pdf, SDH transmission slot Fault Circular. Pdf, SDH transmission network optimization of the clock. Pdf.
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Size: 706560 |
Author: 李宏伟 |
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Description: FPGA的应用，数字交叉连接矩阵的应用，VERILOG的一些应用等-FPGA applications, the application of digital cross-connect matrix, VERILOG some of the applications
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Size: 707584 |
Author: 辛晨 |
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Description: SDH开销的接收处理，要求：
1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。
2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
-Receiving SDH overhead processing requirements: 1, A1 and A2 bytes instruction byte header, A1 is " 11110110" , A2 is " 00101000" , for three consecutive A1 bytes followed by three A2 bytes of an SDH the beginning of the frame. Asked to design a state machine, from the continuous stream of bytes in the SDH transmission header to find out. 2, E2-byte path overhead for the service, then, for the public to contact voice channels, the bit-serial rate 64KHz (8* 8K = 64). SDH byte stream request from the extraction E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock requires 64K basic uniform. (Including the serial data output port and 64K serial clock)
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Size: 2048 |
Author: 刘镇宇 |
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Description: SHD 详细设计,包含各种文档，以及VERILOG 源代码-SHD detailed design, including all documents
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Size: 1778688 |
Author: 徐强 |
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