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Description: 详细的SDRAM控制器HDL代码,最顶层代码,很清晰-detailed SDRAM controller HDL code top-level code, it was very clear
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Size: 2941 |
Author: 陈建勇 |
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Description: SDRAM顶层模块,大家可以看看,学习一下模块的化分
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Size: 1762 |
Author: 大哥 |
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Description: 很好用的!很好用的代码1SDRAM的源码!一定有用
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Size: 1881 |
Author: 陈吉成 |
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Description: 详细的SDRAM控制器HDL代码,最顶层代码,很清晰-detailed SDRAM controller HDL code top-level code, it was very clear
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Size: 3072 |
Author: 陈建勇 |
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Description: SDRAM顶层模块,大家可以看看,学习一下模块的化分-SDRAM module top-level, we will look at and learn about modules of sub-
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Size: 1024 |
Author: 大哥 |
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Description: 很好用的!很好用的代码1SDRAM的源码!一定有用-Good use! Good use of source code 1SDRAM! Certainly useful
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Size: 2048 |
Author: 陈吉成 |
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Description: 文章详细讲述了sdr_sdram控制器的使用和编程思想-sdr_sdram
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Size: 701440 |
Author: chentao |
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Description: 用Verilog实现SDR_SDRAM的控制器,可用FPGA实现对普通SDRAM的读写操作!-SDR_SDRAM using Verilog implementation of the controller, the FPGA can be used to achieve the ordinary SDRAM read and write operations!
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Size: 37888 |
Author: 许文建 |
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Description: sdram控制器顶层模块的VHDL源程序文件,可直接用-sdr SDRAM
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Size: 3072 |
Author: liuzhijun |
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Description: sdram控制器,verilog语言写的-sdram controller, verilog language to write
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Size: 2048 |
Author: xwj |
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Description: SDR SDRAM 控制器,Altera官网重要资料。内涵说明文档,和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
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Size: 2360320 |
Author: peteryu010 |
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Description: 用FPGA实现SDRAM的控制,主要是将SDRAM的时序搞懂,这个很好做出来了。-Using FPGA realize SDRAM control, mainly the SDRAM timing out, this is very good do.
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Size: 2570240 |
Author: hanbo |
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Description: sdram使用接口仿真,altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
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Size: 12288 |
Author: 风雪来 |
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