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[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2008-10-13 Size : 426.81kb Publisher : kevin
[WEB Code] SDRAM-VHDL DL : 0: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Update : 2008-10-13 Size : 122.5kb Publisher : 许春明
[SourceCode] altera sdram controller DL : 1: altera sdram controller vhdl
Update : 2011-03-17 Size : 2.26mb Publisher : langzhongfeilang@126.com
[VHDL-FPGA-Verilog] sdram_vhdl_lattice DL : 0: lattice sdram 控制器VHDL源代码-Sound code of Lattice Sdram Controller based on VHDL
Update : 2025-02-17 Size : 176kb Publisher : 刘汉忠
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2025-02-17 Size : 1007kb Publisher : 包盛花
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] sdr sdram controller DL : 0: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Update : 2025-02-17 Size : 2.34mb Publisher : 陈东平
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[Documents] SDRAM-VHDL DL : 0: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Update : 2025-02-17 Size : 122kb Publisher :
[VHDL-FPGA-Verilog] DDRSDRAM DL : 0: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Update : 2025-02-17 Size : 463kb Publisher : 张宁
[Other] ref-sdr-sdram-verilog DL : 0: sdram控制器的开发程序，还有文档，可以参考以下-SDRAM controller development process, there is a document, you can refer to the following
Update : 2025-02-17 Size : 758kb Publisher : 王鹏
[VHDL-FPGA-Verilog] sdram DL : 0: sdram test controller altera -sdram test controller altera
Update : 2025-02-17 Size : 1.45mb Publisher : yangchun
[VHDL-FPGA-Verilog] DDR_SDRAM_controller DL : 0: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Update : 2025-02-17 Size : 129kb Publisher : xbl
[VHDL-FPGA-Verilog] AlteraSDR-SDRAM DL : 0: Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Update : 2025-02-17 Size : 792kb Publisher : machenghai
[Other] testbench DL : 0: ddr sdram controller datd module source code
Update : 2025-02-17 Size : 3kb Publisher : KrishnaKishore
[VHDL-FPGA-Verilog] sdramctrl DL : 0: sdram controller vhdl
Update : 2025-02-17 Size : 15kb Publisher : wangxiaolong
[Embeded-SCM Develop] hssdrc_latest DL : 0: SDRAM 控制器 Verilog实现，很有借鉴意义。-SDRAM controller core Verilog implementation。With good referential significance.
Update : 2025-02-17 Size : 415kb Publisher : metallica
[VHDL-FPGA-Verilog] sdram_controller DL : 0: It s a SDRAM Controller reference design. It had been tested in many projects.
Update : 2025-02-17 Size : 456kb Publisher : greyzhuang
[Other] SDR-SDRAM-ctl1 DL : 0: SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
Update : 2025-02-17 Size : 702kb Publisher :
[VHDL-FPGA-Verilog] SDRAM-controller-design-FPGA-based DL : 0: 基于FPGA的SDRAM控制器设计及应用硕士论文-SDRAM controller design FPGA based
Update : 2025-02-17 Size : 3.02mb Publisher : connie

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