Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is Verilog.
This code is based Xilinx FPGA Playform. Platform: |
Size: 488448 |
Author:peace |
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Description: DDR-SDRAM接口模块verilog源代码,可用作IP核使用,已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven Platform: |
Size: 474112 |
Author:zyy |
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Description: ALTRA官方提供的SDRAM的控制内核,VHDL和VERILOG版本都有,希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful Platform: |
Size: 2378752 |
Author:mr jiang |
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Description: altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection Platform: |
Size: 2325504 |
Author:杜小方 |
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Description: sdram使用接口仿真,altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method) Platform: |
Size: 12288 |
Author:风雪来 |
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