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[Compress-Decompress algrithms] rd1010_source_code

Description: 使用FPGA做SDRAM控制器 -SDRAM controller using FPGA so
Platform: | Size: 357376 | Author: | Hits:

[Other] testbench

Description: ddr sdram controller datd module source code
Platform: | Size: 3072 | Author: KrishnaKishore | Hits:

[VHDL-FPGA-Verilog] hssdrc_latest.tar

Description: HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
Platform: | Size: 424960 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl

Description: sdram 控制器 含testbench-sdram controller with testbench
Platform: | Size: 29696 | Author: kewell | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] verilog_sdram_controller_testbench

Description: SDRAM 控制器 ，Verilog版本的，带有完整的SDRAM 仿真模型，testbench等，能够实际使用，并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
Platform: | Size: 309248 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] modelsim-sdram-sim

Description: 包括sdram 测试平台，sdram控制器，sdram行为模型。-Includes sdram testbench, sdram controller, sdram behavior model.
Platform: | Size: 186368 | Author: qiubin | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[Other] SDRAM_Modelsim

Description: 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
Platform: | Size: 2521088 | Author: 刘淇 | Hits:

[VHDL-FPGA-Verilog] DDR3-SDRAM-Controller

Description: DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
Platform: | Size: 242688 | Author: 杨凯 | Hits:

[VHDL-FPGA-Verilog] sdram_5

Description: SDRAM的verilog描述，包含顶层设计，测试平台代码，精确描述-SDRAM is verilog description, including top-level design, testbench code, an accurate description of
Platform: | Size: 6144 | Author: micheal zhang | Hits:

[VHDL-FPGA-Verilog] sdram_latest.tar

Description: SDRAM的控制代码，包含文档说话和testbench测试代码-SDRAM control code, including documents speak and testbench test code
Platform: | Size: 587776 | Author: sw | Hits:

[hardware design] sdram_test

Description: 在vivado中用于测试SDRAM，DDR3学习比较有帮助-the testbench for ddr3
Platform: | Size: 4381696 | Author: 史伟忠 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram的控制程序，以及相关的testbench(sdram control module)
Platform: | Size: 128000 | Author: 大地2020 | Hits:

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