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[Other resource] ref-ddr-sdram-vhdl

Description: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Platform: | Size: 1031656 | Author: 包盛花 | Hits:

[Other resource] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Platform: | Size: 1031168 | Author: 包盛花 | Hits:

[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[Other] lattice_sdram_source_code

Description: lattice sdram 控制器的源码，VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
Platform: | Size: 31744 | Author: dido wang | Hits:

[VHDL-FPGA-Verilog] sdram_inf

Description: sdram操作的vhdl源代码，对自己编写SDRAM核有很好的参考意义-SDRAM operation of VHDL source code, the preparation of their own nuclear SDRAM have a good reference value
Platform: | Size: 2048 | Author: 宋军 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 88064 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: 同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用-Synchronous Dynamic RAM control circuit VHDL source code, in the SOC development can be applied directly
Platform: | Size: 90112 | Author: 26 | Hits:

[VHDL-FPGA-Verilog] AlteraSdramIP

Description: Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written
Platform: | Size: 781312 | Author: 张敏 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[VHDL-FPGA-Verilog] sdram_ver_134

Description: SDRAM控制器的源代码打包下载，不错不错值得-SDRAM controller source code pack download, well worth a good try
Platform: | Size: 115712 | Author: jinyong | Hits:

[VHDL-FPGA-Verilog] altera_sdram

Description: Simple SDRAM controller source code for Altera DE2 board
Platform: | Size: 7168 | Author: leblebitozu | Hits:

[Other Embeded program] SDRAM_design_source

Description: sdram的设计文档和参考源码。嵌入式开发中很难找到的源码。-sdram design documents and source code
Platform: | Size: 159744 | Author: wisebear | Hits:

[VHDL-FPGA-Verilog] ddr-sdram

Description: DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
Platform: | Size: 923648 | Author: runxin | Hits:

[VHDL-FPGA-Verilog] sdram-source

Description: SDR SDRAM 控制器的源代码 altera公司的-source code from altera
Platform: | Size: 717824 | Author: wela | Hits:

[VHDL-FPGA-Verilog] source

Description: SDRAM控制器源代码，是ALTERA公司的IP源核，很好很强大-SDRAM controller source code, very very strong
Platform: | Size: 11264 | Author: 张理 | Hits:

[VHDL-FPGA-Verilog] sdr-sdram-controller-source-code

Description: altera 公司sdr sdram 控制器源码，是VHDL的，大家选择下载-The altera sdr sdram controller source, the VHDL, we choose to download
Platform: | Size: 16384 | Author: 梦殇 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram程序源代码 仿真成功 可供学习使用(SDRAM program source code, simulation success, available for learning to use)
Platform: | Size: 8962048 | Author: AYEA | Hits:
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