Search - seg7_lut

[VHDL-FPGA-Verilog] SEG7_LUT_8_0

Description: DE2开发平台7段显示VHDL代码，自己针对vilorg翻译成VHDL代码-DE2 Development Platform 7 show the VHDL code for vilorg translated into their own VHDL code
Platform: | Size: 1024 | Author: siubr | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111001 //---t---- 4 h2: oSEG = 7 b0100100 // | | 4 h3: oSEG = 7 b0110000 // lt rt 4 h4: oSEG = 7 b0011001 // | | 4 h5: oSEG = 7 b0010010 //---m---- 4 h6: oSEG = 7 b0000010 // | | 4 h7: oSEG = 7 b1111000 // lb rb 4 h8: oSEG = 7 b0000000 // | | 4 h9: oSEG = 7 b0011000 //---b---- 4 ha: oSEG = 7 b0001000 4 hb: oSEG = 7 b0000011 4 hc: oSEG = 7 b1000110 4 hd: oSEG = 7 b0100001 4 he: oSEG = 7 b0000110 4 hf: oSEG = 7 b0001110 default: oSEG = 7 b1000000 endcase end endmodule
Platform: | Size: 1024 | Author: 王林林 | Hits:

[Other] SEG7_LUT

Description: altera 7-segment verilog code.
Platform: | Size: 3072 | Author: SongjaeMin | Hits:

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[VHDL-FPGA-Verilog] SEG7_LUT_8_0

[VHDL-FPGA-Verilog] Verilog

[Other] SEG7_LUT

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