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[Other] s2p

Description: 用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好-using VHDL code written in parallel to serial procedures waveform correct, the board has been running that good
Platform: | Size: 99328 | Author: 国宝 | Hits:

[VHDL-FPGA-Verilog] bingzhuanchuan

Description: 这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
Platform: | Size: 1024 | Author: 华涛 | Hits:

[Embeded-SCM Develop] vhdlthreelinespi

Description: ＳＰＩ总线与ＣＰＬＤ之间的通信程序，可实现ＳＰＩ串行输入，通过移位寄存器后并行输出-SPI bus and the CPLD communication between these procedures is to realize SPI serial input, through the shift register parallel output after
Platform: | Size: 1024 | Author: 金臻炜 | Hits:

[Com Port] UARTchuli

Description: UART 处理的是并行数据转换为串行信号和串行信号转换为并行数据。现有的时钟不精确,这就需要用一个远高于波特率的本地时钟信号对输入信号不断采样,以不断让接收器与发送器保持同步。-UART to handle is the parallel data into a serial signal and serial signal is converted to parallel data. Existing imprecise clock, which requires a much higher than the baud rate of the local clock signal for sampling the input signal continuously to continuously allow the receiver to maintain synchronization with the transmitter.
Platform: | Size: 1024 | Author: xuye | Hits:

[ARM-PowerPC-ColdFire-MIPS] jtag_logic

Description: Serial/Parallel converter, interfacing JTAG chain with FTDI FT245BM
Platform: | Size: 2048 | Author: yuxiaoqin | Hits:

[Other] GPSdecoder

Description: 采用状态机完成GPS串口信息GPRMC数据的解析，输出并行的年、月、日、时、分、秒信息，可直接移植。-State machine used to complete GPS information GPRMC serial data analysis, the output parallel year, month, day, hour, minute, second information, can be directly transplanted.
Platform: | Size: 1024 | Author: 杨启勇 | Hits:

[VHDL-FPGA-Verilog] 080513154000

Description: 并行转串行的VHDL描述：基于FPGA的SPI发送模块的设计-Parallel to serial VHDL description: Based on the FPGA to send the SPI module
Platform: | Size: 95232 | Author: yaoqinghua | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

[Com Port] chuankoutongxin

Description: 串口通信的概念非常简单，串口按位（bit）发送和接收字节。尽管比按字节（byte）的并行通信慢，但是串口可以在使用一根线发送数据的同时用另一根线接收数据。它很简单并且能够实现远距离通信。比如IEEE488定义并行通行状态时，规定设备线总常不得超过20米，并且任意两个设备间的长度不得超过2米；而对于串口而言，长度可达1200米。典型地，串口用于ASCII码字符的传输。通信使用3根线完成：（1）地线，（2）发送，（3）接收。由于串口通信是异步的，端口能够在一根线上发送数据同时在另一根线上接收数据。其他线用于握手，但是不是必须的。串口通信最重要的参数是波特率、数据位、停止位和奇偶校验。-The concept of serial communication is very simple, serial by bit (bit) to send and receive bytes. Although more than by byte (byte) of parallel communication slow, but can use a serial line to send data at the same time another line to receive data. It is very simple and can achieve long-distance communications. For example, the definition of IEEE488 parallel access mode, the total line often provides equipment shall not be more than 20 meters, and between any two devices may not be more than two meters in length and in terms of the serial port, up to 1200 meters in length. Typically, serial code for the ASCII character transmission. 3 lines of communication to use to complete: (1) ground, (2) send, (3) to receive. Due to the asynchronous serial communication port to send data in a line at the same time another line to receive data. Other lines for the handshake, but not necessary. Serial communication the most important parameter is the baud rate, data bits, stop bits and parity.
Platform: | Size: 1024 | Author: zhendongzhao | Hits:

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

Description: 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用-String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
Platform: | Size: 1024 | Author: 随风 | Hits:

[Com Port] Receiver

Description: This file recieves the serial data from the UART and forward to Serial To Parallel module
Platform: | Size: 2048 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] code

Description: This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
Platform: | Size: 5120 | Author: RUPA KRISHNA | Hits:

[VHDL-FPGA-Verilog] serial

Description: 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
Platform: | Size: 13312 | Author: tangjieling | Hits:

[VHDL-FPGA-Verilog] piso8

Description: 并/串转换的VHDL源代码，其中包括完整的QUARTUS2工程，还有正确的仿真波形。串行，并行数据 -Serial/parallel conversion ，VHDL source code, including complete QUARTUS2 project, and the correct simulation waveform file.
Platform: | Size: 223232 | Author: simulin_2008 | Hits:

[VHDL-FPGA-Verilog] seriall2parallel

Description: its code for converting serial to parallel processing data
Platform: | Size: 1024 | Author: sundaram | Hits:

[VHDL-FPGA-Verilog] shift16

Description: The data in the shift register in shift pulses can move or by bit right next moves left, data can be parallel input, parallel output, also can serial input, serial output, still can parallel input, output, serial input, serial, parallel output is flexible, use also is very wide.
Platform: | Size: 277504 | Author: 张凯 | Hits:

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

Description: 用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based implementations, there are classic serial algorithm LFSR, circuits and software algorithms derived from the other kinds of parallel computing. To the classic LFSR, circuit-based, study by the CRC byte parallel computing principles.
Platform: | Size: 205824 | Author: Geer | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[Education soft system] 2-bit-parallel-to-serial-conversion-VHDL-source-c

Description: This page of VHDL source code covers 2 bit parallel to serial vhdl code and provides link to 2 bit serial to parallel conversion.
Platform: | Size: 1024 | Author: ss | Hits:

[VHDL-FPGA-Verilog] Serial to parallel vhdl

Description: SERIAL TO PARALLEL VHDL CODE
Platform: | Size: 9216 | Author: kiruthikka | Hits:
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