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[VHDL-FPGA-Verilog] 65jie

Description: 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点，但是要占用大量的资源。在多阶数的亚高频系统设计中，使用并行结构并不合算，但亚高频系统需要较高的处理速度，而串行架构往往达不到要求，因此，结合串并这两种设计方法的长处，在使用较少的硬件资源的同时实现了较高的处理速度，这里说明一种65阶八路并行、支路串行FIR滤波器的设计（实际使用了1个乘法器，8个乘累加器，一个累加器）。-String and FIR filter design: parallel FIR filter with a fast, easy design features, but I want to use up a lot of resources. In a multi-order high-frequency sub-system design, the use of parallel structures and uneconomical, but the high frequency sub-system requires a higher processing speed, and the serial structure often fail, therefore, combines both the design of string and method' s strengths, using less hardware resources to achieve a high processing speed of 65 bands here that a parallel eight-way, slip serial FIR filter design (the actual use of a multiplier, 8 by accumulator, an accumulator).
Platform: | Size: 12288 | Author: 南才北往 | Hits:

[VHDL-FPGA-Verilog] code

Description: This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
Platform: | Size: 5120 | Author: RUPA KRISHNA | Hits:

[Industry research] ADSP-21262

Description: High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)-High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)
Platform: | Size: 507904 | Author: ak | Hits:

[source in ebook] ADSP_2126x_HRM

Description: High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG -High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG
Platform: | Size: 1542144 | Author: ak | Hits:

[VHDL-FPGA-Verilog] robust_fir_latest.tar

Description: RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).-RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).
Platform: | Size: 6144 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] -Elliptic

Description: We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.
Platform: | Size: 116736 | Author: 陳曉慧 | Hits:

[MiddleWare] Serial-parallel-multiplier-verilog-design

Description: Serial parallel multiplier verilog design source code
Platform: | Size: 27648 | Author: dorababugfree | Hits:

[Other] my_multiplier

Description: 一个VHDL编的简单乘法器，基本原理设计如下图所示: 将两个操作数分别以串行和并行模式输入到乘法器的输入端, 用串行输入操作数的每一位依次去乘并行输入的操作数, 每次的结果称之为部分积, 将每次相乘得到的部分积加到累加器里, 形成部分和, 部分和在与下一个部分积相加前要进行移位操作。-A simple multiplier VHDL series, the basic principles of design as follows: two operands, respectively, serial and parallel mode to the input terminal of the multiplier, with every serial input operands in parallel in order to multiply the input operands, the result of each partial product is called, the partial products obtained by multiplying each time to the accumulator, the forming portion, and, prior to the addition portion and with the next partial product is shifted to .
Platform: | Size: 1024 | Author: Justin | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: this a 8-bit Multiplier using 3 stages. after reset the 8 bit operands are loaded and the serial-parallel multiplication takes place.-this is a 8-bit Multiplier using 3 stages. after reset the 8 bit operands are loaded and the serial-parallel multiplication takes place.
Platform: | Size: 193536 | Author: hooman hematkhah | Hits:

[VHDL-FPGA-Verilog] 8-bit-Multiplier

Description: Multiplication is performed in three stages. After reset, the 8-bit operands are “loaded” and the product register is set to zero. In the second stage, s1, the actual serial-parallel multiplication takes place. In the third step, s2, the product is transferred to the output register y.
Platform: | Size: 193536 | Author: hooman hematkhah | Hits:

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