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[Other] ask10

Description: This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.
Platform: | Size: 2048 | Author: thesky | Hits:

[Embeded-SCM Develop] simplemips

Description: simple MIPS with verilog
Platform: | Size: 56320 | Author: hwiparam | Hits:

[Other Embeded program] mips_single

Description: 這是以verilog所撰寫的MIPS single CPU文件檔。可完成簡單的加減運算。 -This is the verilog are written in MIPS single CPU document file. To be completed by the simple addition and subtraction.
Platform: | Size: 5120 | Author: Brandon | Hits:

[ARM-PowerPC-ColdFire-MIPS] SCMIPS

Description: 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
Platform: | Size: 134144 | Author: 赵成龙 | Hits:

[Other] code

Description: 是用verilog写的带uart的简单controller，使用的是mips指令，用modelsim仿真，波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
Platform: | Size: 72704 | Author: 张三 | Hits:

[Other] cache

Description: 基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
Platform: | Size: 117760 | Author: 邹楠 | Hits:

[Software Engineering] 3proyectodig-WinRAR-ZIP

Description: a simple unicycle mips preocessor in verilog
Platform: | Size: 3811328 | Author: zener | Hits:

[Other] multi_cpu

Description: 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
Platform: | Size: 1635328 | Author: chenjy | Hits:

[VHDL-FPGA-Verilog] cpu_design

Description: FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Platform: | Size: 2428928 | Author: leo | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
Platform: | Size: 12288 | Author: 胡森 | Hits:

[VHDL-FPGA-Verilog] MIPS

Description: 用verilog编写的简单的类MIPS多周期流水化处理器实现，基本功能包括9条指令和两位动态分支预测，压缩包里的word详细说明了结构中的细节-Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies the details of the structure
Platform: | Size: 239616 | Author: csy | Hits:

[Windows Develop] wuhao

Description: C语言编程以及MIPS汇编语言还有logisim的简单实现，算法(C language programming and MIPS assembly language, as well as a simple implementation of logisim, algorithm)
Platform: | Size: 2514944 | Author: welkin1027 | Hits:

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