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[SCM] DPRamComm

Description: 基于双口RAM的单片机间通信 从书上摘抄的，仅供参考-Based on the single-chip dual-port RAM communication excerpt from the book, and for reference only
Platform: | Size: 2048 | Author: sun | Hits:

[SCM] DPRam_Comm

Description: 基于双口RAM的单片机间通信 从书上摘抄的，仅供参考-Based on the single-chip dual-port RAM communication excerpt from the book, and for reference only
Platform: | Size: 2048 | Author: sun | Hits:

[SCM] 25

Description: 基于双口RAM的单片机间通信-Based on the single-chip dual-port RAM communication
Platform: | Size: 22528 | Author: peter | Hits:

[VHDL-FPGA-Verilog] bram_delay

Description: Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
Platform: | Size: 1438720 | Author: niuniu | Hits:

[VHDL-FPGA-Verilog] memory_cores

Description: 通用ram源码包，包括双口ram，单口ram，fifo等-general ram source package，include dual port ram，single port ram，fifo，etc.
Platform: | Size: 36864 | Author: 东 | Hits:

[VHDL-FPGA-Verilog] ex9_cof_M4K_test1

Description: 这是一个基于M4K块得单口RAM配置仿真实验程序-This is an M4K block was based on a single-port RAM configuration simulation program
Platform: | Size: 4319232 | Author: cpu | Hits:

[VHDL-FPGA-Verilog] Single-port-RAM-

Description: 单口RAM带CLR信号的verilog程序。很详细的.-Single-port RAM with a CLR signal
Platform: | Size: 1118208 | Author: 赵峰 | Hits:

[VHDL-FPGA-Verilog] ram

Description: ram single-port RAM in write-first mode.
Platform: | Size: 9216 | Author: chai | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: single-port RAM in write-first mode. module raminfr (clk, we, en, addr, di, do) input clk input we input en input [4:0] addr input [3:0] di output [3:0] do reg [3:0] RAM [31:0] reg [4:0] read_addr always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di read_addr <= addr end end assign do = RAM[read_addr] endmodule -single-port RAM in write-first mode. module raminfr (clk, we, en, addr, di, do) input clk input we input en input [4:0] addr input [3:0] di output [3:0] do reg [3:0] RAM [31:0] reg [4:0] read_addr always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di read_addr <= addr end end assign do = RAM[read_addr] endmodule
Platform: | Size: 32768 | Author: chai | Hits:

[VHDL-FPGA-Verilog] ram_sp_ar_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] ram_sp_sr_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] spram

Description: 基于altera fpga 的单口ram ip核的应用实例，包含整个工程和moselsim仿真，数据，写使能，地址都是用模块来产生的。-Altera fpga single port ram the ip core application instance, contains the entire engineering and moselsim of simulation data, Write Enable, addresses are generated by the module.
Platform: | Size: 2859008 | Author: | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 基于verilog的双口和单口RAM的实现-Verilog dual port and single port RAM-based implementation
Platform: | Size: 137216 | Author: xinghe | Hits:

[VHDL-FPGA-Verilog] RAM

Description: altera FPGA上的RAM源码 单端口结构 -the RAM the source single port structure altera FPGA
Platform: | Size: 731136 | Author: lenovo | Hits:

[VHDL-FPGA-Verilog] single_port_ram_with_init

Description: Single-port RAM with single read/write address and initial contents
Platform: | Size: 1024 | Author: Trung | Hits:

[VHDL-FPGA-Verilog] single_port_ram

Description: Single port RAM with single read/write addre-Single port RAM with single read/write address
Platform: | Size: 1024 | Author: Trung | Hits:

[VHDL-FPGA-Verilog] DistRAM

Description: Distributed Single Port RAM
Platform: | Size: 2048 | Author: hadimk | Hits:

[VHDL-FPGA-Verilog] single_port_ram

Description: Single port RAM file VHDL source code
Platform: | Size: 35840 | Author: mitch | Hits:

[Wavelet] storage1_8_16

Description: 8x16 single port ram
Platform: | Size: 2048 | Author: hojin | Hits:

[File Format] ug_ram_rom

Description: This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP cores to implement the memory modes—the ALTSYNCRAM and ALTDPRAM IP cores. The Quartus® II software automatically selects one of these IP cores to implement memory modes. The selection depends on the target device, memory modes, and features of the RAM and ROM.-This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP cores to implement the memory modes—the ALTSYNCRAM and ALTDPRAM IP cores. The Quartus® II software automatically selects one of these IP cores to implement memory modes. The selection depends on the target device, memory modes, and features of the RAM and ROM.
Platform: | Size: 593920 | Author: nacer1606 | Hits:
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