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[VHDL-FPGA-VerilogCAN_IP

Description: 这是CAN总线控制器的IP核,源码是由Verilog HDL编写的。其硬件结构与SJA1000类似,满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-VerilogEPM570

Description: 介绍epm570在信号采集时候的一个例子,是给予图像采集中的作用,很使用的一个例子。-Introduction epm570 signal acquisition at the time of an example are given to the role of image acquisition, it is used in a case in point.
Platform: | Size: 82944 | Author: 王立新 | Hits:

[ARM-PowerPC-ColdFire-MIPS43680503pxa255_cpld

Description: cpld 驱动sja1-cpld sja1000
Platform: | Size: 1005568 | Author: huangxing | Hits:

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